Features - Freescale Semiconductor MPC850 User Manual

Mpc850 family integrated communications microprocessor
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Chapter 8
Memory Management Unit
The MPC850 implements a virtual memory management scheme that provides cache
control, memory access protections, and effective-to-physical (real) address translation.
The MMU largely complies with the PowerPC operating environment architecture (OEA)
with respect to architecturally defined memory management features that are appropriate
for this implementation. It does not support some PowerPC MMU features more
appropriate for a personal computer that is expected to run many applications
simultaneously, and in some cases provides greater flexibility than is defined by the
PowerPC architecture, especially with respect to page sizes. Available protection
granularity is 4-, 16-, 512-Kbyte, or 8-Mbyte pages or 1-Kbyte subpages (for 4-Kbyte
pages only). The MPC850 has separate instruction and data MMUs. The prefix Mx_
indicates a reference to both the instruction and data (MI_ and MD_) versions of the
register. The MMU supports two protection modes—PowerPC mode with extended
encoding and domain manager mode, which provides programmable overrides to page
protection settings.

8.1 Features

The following is a list of the MMU's important features:
• Multiple page sizes—4-, 16-, 512-Kbyte, or 8-Mbyte pages (optional 1-Kbyte
subpage protection granularity for 4-Kbyte pages) with the following page
attributes:
— Changed bit support through the DTLB error exception on a write attempt to a
unmodified page (data MMU only)
— Write-through attribute for data accesses
— Cache-inhibit attribute for data and instruction accesses
— Default write-through and cache-inhibited attributes can be programmed for
when translation is disabled
— Guarded attribute for memory-mapped I/O and other nonspeculative regions
• Instruction and data address translation can be disabled separately
• MPC850-specific special-purpose registers (SPRs) accessible with the PowerPC
mfspr/mtspr instructions
• Supports up to 16 virtual address spaces
Chapter 8. Memory Management Unit

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