Debug Mode Registers; Interrupt Cause Register (Icr) - Freescale Semiconductor MPC850 User Manual

Development Support Programming Model
Table 44-23 describes COUNTA and COUNTB fields.
Table 44-23. COUNTA/COUNTB Field Descriptions
Bits
0–15
16–29
30–31

44.5.2 Debug Mode Registers

The debug registers are described in the following sections.

44.5.2.1 Interrupt Cause Register (ICR)

The ICR indicates the reason that debug mode was entered. ICR bits are set by the hard-
ware and cleared when the register is read. Attempts to write to ICR are ignored. All bits
are cleared when exiting reset.
Bit 0 1 2
Field — RST CHSTP
Bit 16 17 18
Field — SEI ITLBMS DTLBMS ITLBER DTLBER
Reset
R/W
SPR
ICR protection is described in Table 44-15. Table 44-24 describes ICR fields.
Bits Name
0 — Reserved
1 RST Reset interrupt bit. Set when the SRESET is asserted.
2 CHSTP Check stop bit. Set when the machine check interrupt is asserted and MSR[ME] = 0. Results in
debug mode entry if debug mode is enabled and the corresponding enable bit is set. Otherwise,
the processor enters checkstop state.
3 MCI Machine check interrupt bit. Set when the machine check interrupt is asserted and MSR[ME] =1.
Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set.
4–5 — Reserved
6 EXTI External interrupt bit. Set when the external interrupt is asserted. Causes debug mode entry if
debug mode is enabled and the corresponding enable bit is set.
Name
CNTV Counter preset value
— Reserved
CNTC Counter source select
00 Not active (reset value)
01 Instruction first (COUNTA)/second (COUNTB) watchpoint
10 Load/store first (COUNTA)/second (COUNTB) watchpoint
11 Reserved
3 4 5
MCI —
19 20 21
0000_0000_0000_0000
Figure 44-22. Interrupt Cause Register (ICR)
Table 44-24. ICR Field Descriptions
MPC850 Family User's Manual
Description
6 7 8 9 10
EXTI ALI PRI FPUVI DECI
22 23 24 25 26
—
R/W
148
Description
11 12 13 14 15
— SYSI TR —
27 28 29 30 31
LBRK IBRK EBRK DPI