Development Support Registers; Comparator A–H Value Registers (Cmpa–Cmph) - Freescale Semiconductor MPC850 User Manual

Table 44-15. Development Support/Debug Registers Protection
Operation MSR[PR]
Read 0
register
0
0
1
Write 0
register
0
0
1

44.5.1 Development Support Registers

The following sections describe the development support registers.
44.5.1.1 Comparator A–H Value Registers (CMPA–CMPH)
The comparator value registers (CMPA–CMPH) hold the instruction and data to be used in
comparisons. Figure 44-14 shows CMPA–CMPD, which are used for instruction address
bus comparisons. Because instructions are 32 bits wide (word), bits 30–31 are not used.
Bit 0 1 2
Field
Reset
R/W
SPR
Figure 44-14. Comparator A–D Value Register (CMPA–CMPD)
Table 44-16 describes CMPA–CMPD fields.
Bits
0–29
30–31
Debug Mode In Debug
Enable Mode
0 X
1 0
1 1
X X
0 X
1 0
1 1
X X
3 4 5
144 (CMPA), 145 (CMPB), 146 (CMPC), 147 (CMPD)
Table 44-16. CMPA–CMPD Field Descriptions
Name
CMPV Address bits to be compared.
— Reserved.
Chapter 44. System Development and Debugging
Development Support Programming Model
Read is performed. (When reading ICR, it is also cleared.)
Read is performed. (When reading ICR, it is not cleared.)
Read is performed. (When reading ICR, it is also cleared.)
Read is not performed, program interrupt is generated. (When
reading ICR, it is not cleared.)
Write is performed. (Write to ICR or DPDR is ignored, the
register is not modified and no interrupt is generated.)
Write is ignored.
Write is performed. (Write to ICR is ignored, the register is not
modified and no interrupt is generated.)
Write is not performed, program interrupt is generated.
6 ...
CMPV
Undefined
R/W
Description
Result
29 30 31
—