Single-Beat Read Flow - Freescale Semiconductor MPC850 User Manual

Bus Operations

13.4.2.1 Single-Beat Read Flow

The basic read cycle begins with a bus arbitration, followed by the address transfer, then the
data transfer. The following flow and timing diagrams show the handshakes applicable to
the fixed transaction protocol.
MASTER SLAVE
Bus Request (BR)
Receives Bus Grant (BG) from arbiter
Asserts Bus Busy (BB) if no other master is driving
Asserts Transfer Start (TS)
Drives address and attributes
Receives Address
Returns data
Asserts Transfer Acknowledge (TA)
Receives data
Figure 13-4. Basic Flow Diagram of a Single-Beat Read Cycle
Chapter 13. External Bus Interface