Memory Control Instructions—Vea; Powerpc Oea Instructions - Freescale Semiconductor MPC850 User Manual

5.2.5.3 Memory Control Instructions—VEA
Memory control instructions include the following types:
• Cache management instructions
• Translation lookaside buffer (TLB) management instructions
This section describes the user-level cache management instructions defined by the VEA.
See Section 5.2.6.3, "Memory Control Instructions—OEA," for information about
supervisor-level cache and translation lookaside buffer management instructions.
The instructions listed in Table 5-19 provide user-level programs the ability to manage
on-chip caches.
As with other memory-related instructions, the effect of the cache management instructions
on memory are weakly ordered. If the programmer needs to ensure that cache or other
instructions have been performed with respect to all other processors and system
mechanisms, a sync instruction must be placed in the program following those instructions.
Note that when data address translation is disabled (MSR[DR] = 0), the Data Cache Block
Set to Zero (dcbz) instruction allocates a cache block in the cache and may not verify that
the physical address is valid. If a cache block is created for an invalid physical address, a
machine check condition may result when an attempt is made to write that cache block back
to memory. The cache block could be written back as a result of the execution of an
instruction that causes a cache miss and the invalid addressed cache block is the target for
replacement or a Data Cache Block Store (dcbst) instruction.
Table 5-19 lists the cache instructions that are accessible to user-level programs.
Name
Data Cache Block Touch
Data Cache Block Touch for
Store
Data Cache Block Set to
Zero
Data Cache Block Store
Data Cache Block Flush
Instruction Cache Block
Invalidate

5.2.6 PowerPC OEA Instructions

The PowerPC OEA includes the structure of the memory management model,
supervisor-level registers, and the exception model.
Table 5-19. User-Level Cache Instructions
Mnemonic Syntax
dcbt rA,rB
dcbtst rA,rB
dcbz rA,rB
dcbst rA,rB
dcbf rA,rB
icbi rA,rB
Chapter 5. MPC850 Instruction Set
MPC850 Notes
The appropriate cache block is checked for a hit. If it is a miss,
the instruction is treated as a regular miss, except that bus
error does not cause an exception. If no error occurs, the
cache is updated.
Executes as defined in the VEA.
Executes as defined in the VEA.
Executes as defined in the VEA.
The MMU translates the EA and the associated instruction
cache block is invalidated if hit.
Instruction Set Summary