Handling Errors In The Smc Uart Controller; Smc Uart Receive Bd (Rxbd) - Freescale Semiconductor MPC850 User Manual

SMC in UART Mode
sequence is sent, data from two ready transmit buffers can be sent on the transmit pin with
no delay between them.

30.3.9 Handling Errors in the SMC UART Controller

The SMC UART controller reports character reception errors via the channel RxBD status
fields and the SMC event register (SMCE). Table 30-7 shows the possible UART receiving
errors. The SMC UART controller has no transmission errors.
Error
Overrun The SMC maintains a two-character length FIFO for receiving data. Data is moved to the buffer after the
first character is received into the FIFO; if a receiver FIFO overrun occurs, the channel writes the
received character into the internal FIFO. It then writes the character to the buffer, closes it, sets
RxBD[OV], and generates the RX interrupt if it is enabled. Reception then resumes as normal.
Overrun errors that occasionally occur when the line is idle can be ignored.
Parity The channel writes the received character to the buffer, closes it, sets the PR bit in the BD, and
generates the RX interrupt if it is enabled. Reception then resumes as normal.
Idle An idle is found when a character of all ones is received, at which point the channel counts consecutive
Sequence idle characters. If the count reaches MAX_IDL, the buffer is closed and an RX interrupt is generated. If
Receive no receive buffer is open, this does not generate an interrupt or any status information. The idle counter
is reset each time a character is received.
Framing The SMC received a character with no stop bit. When it occurs, the channel writes the received
character to the buffer, closes the buffer, sets FR in the BD, and generates the RX interrupt if it is
enabled. When this error occurs, parity is not checked for the character.
Break The SMC receiver received an all-zero character with a framing error. The channel increments BRKEC,
Sequence generates a maskable BRK interrupt in SMCE, measures the length of the break sequence, and stores
this value in BRKLN. If the channel was processing a buffer when the break was received, the buffer is
closed with the BR bit in the RxBD set. The RX interrupt is generated if it is enabled.

30.3.10 SMC UART Receive BD (RxBD)

The CP reports information about the received data in each buffer's RxBD, shown in
Figure 30-6. The CP then closes the current buffer, generates a maskable interrupt, and
starts receiving data into the next buffer after one of the following occurs:
• An error is received during message processing
• A full receive buffer is detected
• A programmable number of consecutive idle characters are received
0 1
Offset + 0 E —
Offset + 2
Offset + 4
Offset + 6
Table 30-7. SMC UART Errors
2 3 4 5
W I — CM
Figure 30-6. SMC UART Receive BD (RxBD)
MPC850 Family User's Manual
Description
6 7 8 9 10
ID — BR
Data Length
Rx Buffer Pointer
11 12 13 14
FR PR — OV
15
—