Programming The Scc Hdlc Controller; Scc Hdlc Commands - Freescale Semiconductor MPC850 User Manual

Figure 23-2 shows 16- and 8-bit address recognition.
Flag Address
0x7E 0x68
Recognizes one 16-bit address (HADDR1) and
the 16-bit broadcast address (HADDR2)

23.5 Programming the SCC HDLC Controller

HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. The HDLC
controller uses the same buffer and BD data structure as other modes and supports
multibuffer operation and address comparisons. Receive errors are reported through the
RxBD; transmit errors are reported through the TxBD.

23.6 SCC HDLC Commands

The transmit and receive commands are issued to the CPM command register (CPCR).
Transmit commands are described in Table 23-2.
Command
After a hardware or software reset and a channel is enabled in the GSMR, the transmitter starts polling
STOP
the first BD in the TxBD table every 64 Tx clocks, or immediately if TODR[TOD] = 1, and begins sending
TRANSMIT
data if TxBD[R] is set. If the SCC receives the
transmitter stops polling the BDs. If the SCC receives the command during transmission, transmission is
aborted after a maximum of 64 additional bits, the Tx FIFO is flushed, and the current BD pointer TBPTR
is not advanced (no new BD is accessed). The transmitter then sends an abort sequence (0x7F) and
stops polling the BDs.
When not transmitting, the channel sends flags or idles as programmed in the GSMR.
Note that if PSMR[MFF] = 1, multiple small frames could be flushed from the Tx FIFO; a
command prevents this.
TRANSMIT
Stops transmission smoothly. Unlike a
GRACEFUL
frame is finished or immediately if no frame is being sent. SCCE[GRA] is set when transmission stops.
STOP
HDLC Tx parameters and Tx BDs can then be updated. TBPTR points to the next TxBD. Transmission
TRANSMIT
begins once TxBD[R] of the next BD is set and a
Enables frames to be sent on the transmit channel. The HDLC controller expects this command after a
RESTART
TRANSMIT STOP TRANSMIT
command, or after a transmitter error. The transmitter resumes from the current BD.
Resets the Tx parameters in the parameter RAM. Issue only when the transmitter is disabled.
INIT TX
PARAMETERS AND RX PARAMETERS
16-Bit Address Recognition
Address Control
0xAA 0x44
HMASK 0xFFFF
HADDR1 0xAA68
HADDR2 0xFFFF
HADDR3 0xAA68
HADDR4 0xAA68
Figure 23-2. HDLC Address Recognition
Table 23-2. Transmit Commands
is issued and the channel in its GSMR is disabled, after a
resets both Tx and Rx parameters.
Chapter 23. SCC HDLC Mode
Programming the SCC HDLC Controller
etc.
Recognizes a single 8-bit address (HADDR1)
Description
command while not transmitting, the
STOP TRANSMIT
command, it stops transmission after the current
STOP TRANSMIT
RESTART TRANSMIT
8-Bit Address Recognition
Flag Address Control
0x7E 0x55 0x44
HMASK 0x00FF
HADDR1 0xXX55
HADDR2 0xXX55
HADDR3 0xXX55
HADDR4 0xXX55
GRACEFUL STOP
command is issued.
GRACEFUL STOP TRANSMIT
etc.
INIT TX