Baud Rate Generator Configuration Registers (Brgcn) - Freescale Semiconductor MPC850 User Manual

Baud Rate Generators (BRGs)
20.4.1 Baud Rate Generator Configuration Registers
(BRGCn)
Each baud rate generator configuration register (BRGC), shown in Figure 20-27, is cleared
at reset. A reset disables the BRG and drives the BRGO output clock high. The BRGC can
be written at any time with no need to disable the SCCs or external devices that are
connected to BRGO. Configuration changes occur at the end of the next BRG clock cycle
(no spikes occur on the BRGO output clock). BRGC can be changed on-the-fly; however,
two changes should not occur within a time equal to two source clock periods.
Bit 0 1
Field
Reset
R/W
Addr
Bit 16 17
Field EXTC
Reset
R/W
Addr
Figure 20-27. Baud Rate Generator Configuration Registers (BRGCn)
Table 20-13 describes the BRGCn fields.
Bits Name
0–13 — Reserved, should be cleared.
14 RST Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset
disables the BRG and drives BRGO high. This is externally visible only if BRGO is connected to the
corresponding parallel I/O pin.
0 Enable the BRG.
1 Reset the BRG (software reset).
15 EN Enable BRG count. Used to dynamically stop the BRG from counting—useful for low-power modes.
0 Stop all clocks to the BRG.
1 Enable clocks to the BRG.
16–17 EXTC External clock source. Selects the BRG input clock.
00 BRGCLK (internal clock generated by the clock synthesizer in the SIU).
01 CLK2
10 CLK4
11 Reserved.
2 3 4 5
0x9F0 (BRGC1), 0x9F4 (BRGC2), 0x9F8 (BRGC3), 0x9FC (BRGC4)
18 19 20 21
ATB
0x9F2 (BRGC1), 0x9F6 (BRGC2), 0x9FA (BRGC3), 0x9FE (BRGC4)
Table 20-13. BRGCn Field Descriptions
MPC850 Family User's Manual
6 7 8 9
—
0
R/W
22 23 24 25
CD
0
R/W
Description
10 11 12 13
RST
26 27 28 29
14 15
EN
30 31
DIV16