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the implementation of V.24, X.21, and X.21 bis protocols with help from other
general-purpose I/O signals. To configure a port C signal as a CTS or CD signal that
connects to the SCC and generates interrupts, follow these steps:
1. Write the corresponding PCPAR bit with a 0.
2. Write the corresponding PCDIR bit with a 0.
3. Write the corresponding PCSO bit with a 1.
4. Set the PCINT bit to determine which edges cause interrupts.
5. Write the corresponding CIMR bit with a 1 so that interrupts can be sent to the core.
6. The signal value can be read at any time using the PCDAT register.
After connecting CTS or CD to the SCC, choose normal operation mode in GSMR[DIAG]
to enable or disable SCC transmission and reception with these signals.
PC14 and PC15 can be programmed to assert special requests directly to the CPM by
setting RCCR[EIE]; however, do not do so unless instructed by a Motorola-supplied RAM
microcode package.
For IDMA, PC14 and PC15 can be programmed to function as external DMA request
(DREQx) signals. Do not configure PC14and PC15 as DREQ1 and DREQ0 unless IDMA
is initialized; otherwise, erratic operation can occur.
34.4.1 Port C Registers
Port C is supported by five registers. The port C interrupt control register (PCINT) defines
how changes on the signal cause interrupts when they are generated with that signal. The
port C special options register (PCSO) determines whether certain port C signals can
connect to on-chip peripherals and generate an interrupt at the same time. The remaining
port C registers (PCDAT, PCDIR, and PCPAR) have the same functions as their
counterparts on ports A and B. Port C has no open-drain capability.
34.4.1.1 Port C Data Register (PCDAT)
When read, the port C data (PCDAT) register always reflects the current status of each line.
Bit
0
1
Field
—
Reset
R/W
Addr
2
3
4
5
Figure 34-11. Port C Data Register (PCDAT)
Chapter 34. Parallel I/O Ports
6
7
8
9
10
D4–D15
0
R/W
0x966
Port C
11
12
13
14
15
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