A.1 Byte Ordering Overview; A.2 Mpc850 Byte-Ordering Mechanisms - Freescale Semiconductor MPC850 User Manual

Appendix A
Byte Ordering
The MPC850 supports three byte-ordering conventions—big-endian (BE), true
little-endian (TLE), and PowerPC™ architecture little-endian (PPC-LE). This chapter
describes each of the three endian modes. Chapter 3, "Operand Conventions," in PowerPC
Microprocessor Family: The Programming Environments for 32-bit Microprocessors ,
provides a general overview of byte ordering and describes byte ordering for PowerPC
microprocessors.

A.1 Byte Ordering Overview

For big-endian byte ordering, the most-significant byte (MSB) is stored at the lowest
address while the least-significant byte (LSB) is stored at the highest address. This is called
big-endian because the big end of the scalar comes first in memory.
For true little-endian byte ordering, the LSB is stored at the lowest address while the MSB
is stored at the highest address. This is called true little-endian because the little end of the
scalar comes first in memory.
For PowerPC little-endian byte ordering (also referred to as 'munged little-endian'), the
address of data is modified so that the memory structure appears little-endian to the
executing processor, when in fact, the byte ordering is big-endian. The address modification
is called 'munging'. Note that the term 'munging' is not defined or used in the PowerPC
architecture specification. However, the term is commonly used to describe address
modifications. The byte ordering is called PowerPC little-endian because PowerPC
microprocessors use this method to operate in little-endian mode.

A.2 MPC850 Byte-Ordering Mechanisms

There are several byte-ordering mechanisms in the MPC850 that are controlled by
programmable parameters. The MSR[LE] and MSR[ILE] bits control a 3-bit address
modifier in the PowerPC core. The DC_CST[LES] bit controls a 2-bit address modifier in
the core and a 2-bit address modifier and byte lane swapper in the SIU. The FCR[BO] field
2
of each peripheral (SCCs, SMCs, SPI, I C, PIP, or IDMA) controls a 3-bit address modifier
in the SDMA. Table A-1 correlates the programmable parameters with the byte-ordering
modes of operation.
Appendix A. Byte Ordering