Hdlc Bus Features; Accessing The Hdlc Bus - Freescale Semiconductor MPC850 User Manual

23.14.1 HDLC Bus Features

The main features of the HDLC bus are as follows:
• Superset of the HDLC controller features
• Automatic HDLC bus access
• Automatic retransmission in case of collision
• May be used with the NMSI or a TDM bus
• Delayed RTS mode

23.14.2 Accessing the HDLC Bus

The HDLC bus protocol ensures orderly bus control when multiple transmitters attempt
simultaneous access. The transmitter sending a zero bit at the time of collision completes
the transmission. If a station sends out an opening flag (0x7E) while another station is
already sending, the collision is always detected within the first byte, because the
transmission in progress is using zero bit insertion to prevent flag imitation.
While in the active condition (ready to transmit), the HDLC bus controller monitors the bus
using CTS. It counts the one bits on CTS. When eight consecutive ones are counted, the
HDLC bus controller starts transmitting on the line; if a zero is detected, the internal
counter is cleared. During transmission, data is continuously compared with the external
bus using CTS. CTS is sampled halfway through the bit time using the rising edge of the
Tx clock. If the transmitted bit matches the received CTS bus sample, transmission
continues. However, if the received CTS sample is 0 and the transmitted bit is 1,
transmission stops after that bit and waits for an idle line before attempting retransmission.
Since the HDLC bus uses a wired-OR scheme, a transmitted zero has priority over a
transmitted 1. Figure 23-12 shows how CTS is used to detect collisions.
TCLK
TXD
(Output)
CTS
(Input)
Figure 23-12. Detecting an HDLC Bus Collision
CTS sampled at halfway point.
Collision detected when
TXD=1, but CTS=0.
Chapter 23. SCC HDLC Mode
HDLC Bus Mode with Collision Detection