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44.3.2.1.4 Freeze
The freeze indication means that the processor is in debug mode (normal processor
execution of user code is frozen). Freeze state is indicated on FRZ and is generated
synchronously to the system clock. This indication can be used to halt any off-chip device
while in debug mode and is a handshake between the debug tool and port. In addition to
FRZ, the freeze state is indicated by the value 0b11 on VFLS[0–1], shown in Figure 44-8.
VFLS0 • 1
GND • 3
GND • 5
HRESET • 7
V
• 9
DD
Figure 44-8. Development Port/BDM Connector Pinout Options
Internal freeze status can also be monitored through status in the data shifted out of the
debug port.
44.3.2.2 Development Port Registers
The development port consists logically of three registers:
• The trap enable control register (TECR)
• The development port instruction register (DPIR)
• Development port data register (DPDR)
DPIR and DPDR are both implemented as the development port shift register, which also
acts as a temporary holding register for data to be stored in the TECR.
44.3.2.2.1 Development Port Shift Register
Instructions and data are serially shifted into the 35-bit development port shift register from
the DSDI. DSCK or CLKOUT is the shift clock, depending on the debug port clock mode.
See Section 44.3.2.3, "Development Port Serial Communications–Clock Mode."
The instructions or data are then transferred in parallel to the core and TECR. When the
processor enters debug mode it fetches instructions from DPIR that cause an access to the
development port shift register. These instructions are serially loaded into the shift register
from DSDI using DSCK or CLKOUT as the shift clock. Similarly, data is transferred to the
core. Data is shifted into the shift register and read by the processor by executing
mfspr[DPDR]. Data is also parallel loaded into the development port shift register from
the core by executing mtspr[DPDR]. It is then serially shifted out to DSDO using DSCK
or CLKOUT as the shift clock.
2 • SRESET
4 • DSCK
6 • VFLS1
8 • DSDI
10 • DSDO
Chapter 44. System Development and Debugging
Development System Interface
FRZ • 1
2 • SRESET
GND • 3
4 • DSCK
GND • 5
6 • FRZ
HRESET • 7
8 • DSDI
V
• 9
10 • DSDO
DD
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