The Ram Array; Ram Words - Freescale Semiconductor MPC850 User Manual

15.6.4 The RAM Array

The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in Figure
15-38. The signals at the bottom of Figure 15-38 are UPM outputs. The selected CS is for
the bank that matches the current address. The selected BS is for the byte lanes read or
written by the access.
GCLK1_50
GCLK2_50
CS Signal
Selected Bank
Figure 15-38. RAM Array and Signal Generation
Each UPM request (except software requests issued via
special address that specifies the beginning of the associated pattern in the UPM RAM
array. Table 15-13 shows start addresses of the UPM RAM words for each request type.
(See also Figure 15-32.)
Read single beat cycle (RSS)
Read burst cycle (RBS)
Write single beat cycle (WSS)
Write burst cycle (WBS)
Periodic timer request (PTS)
Exception (EXS)

15.6.4.1 RAM Words

The RAM word, shown in Figure 15-39, is a 32-bit microinstruction stored in one of 64
locations in the RAM array. It specifies timing for external signals controlled by the UPM.
32-Bits Wide
RAM Array
Signals Timing Generator
CS
Selector
CS[0–7] GPL0 GPL1 GPL2 GPL3 GPL4 GPL5
Table 15-13. UPM Start Address Locations
Request to Be Serviced
Chapter 15. Memory Controller
User-Programmable Machines (UPMs)
64 RAM
Words Deep
BS
BS Signal
Selector
BS[0–3]
commands in MCR) has a
RUN
UPM Start Address
0x00
0x08
0x18
0x20
0x30
0x3C
TSIZ, PS, A[30–31]