Memory Bank Protection Status - Freescale Semiconductor MPC850 User Manual

Chip-Select Programming Common to the GPCM and UPM
Table 15-2. Access Granularities for Predefined Port Sizes
Predefined
Port Size
Odd
8-bit
16-bit
32-bit
15.3.6 Parity Configuration
If BRx[PARE] is set, parity is generated and checked (for internal masters only) on a
per-byte basis using DP[0–3] for the bank. As described in Section 10.4.2, "SIU Module
Configuration Register (SIUMCR)," SIUMCR[OPAR] determines the type of parity. Any
parity error causes an internal transfer error indication to be asserted and the associated
MSTAT[PER] and the corresponding TESR[DPB] or TESR[IPB] to be set, as described in
Section 10.4.4, "Transfer Error Status Register (TESR)."

15.3.7 Memory Bank Protection Status

The memory controller status register (MSTAT) reports write-protect violations and parity
errors for all eight banks. This protection provided through BRx[WP], is intended for
detection of erroneous accesses made by DMA from peripherals. More sophisticated
protection is provided for accesses from the core by the MMU, as described in Chapter 8,
"Memory Management Unit."
15.3.8 UPM-Specific Registers
The machine x mode registers (MxMR) define most of the global features for UPMs. The
memory command and memory data registers (MCR and MDR) are used to initialize the
UPM's RAM array. MCR[MAD] is the index into the 64-word RAM array for the MDR.
The memory address register (MAR) specifies the address to be driven on the external bus
when a UPM pattern is software-initiated by issuing a
The memory periodic timer prescaler register (MPTPR) defines the divisor of the external
bus clock used as the memory periodic timer input.
15.3.9 GPCM-Specific Registers
There are no GPCM-specific registers. All GPCM characteristics are defined in the
subfields of individual BRx and ORx registers.
Bytes
Even
√ √
√ √
√ √
MPC850 Family User's Manual
Half Words
Odd Even
— —
— √ (on D[0–15])
√ √
command in the MCR.
RUN
Words (on Word
Boundaries)
—
—
√