Address Compression Example; Preventing Channel Aliasing - Freescale Semiconductor MPC850 User Manual

Address Mapping

39.1.2.3 Address Compression Example

Figure 39-2 shows an example of address compression. The first-level mask (FLMASK)
selects the third PTI bit and five VPI bits. Bitwise ANDing of the FLMASK with the GFC,
VPI, and PTI bits results in a 6-bit pointer. Pointer1 turns out to equal 0x3, and therefore is
pointing to the fourth entry of the FLT. The entry contains a 16-bit mask (SLMASK) for the
VCI field, and the second-level table offset (SLTOFFSET) pointing to one of the SLTs. The
VCI is masked with SLMASK, resulting in a 7-bit pointer to the assigned channel number
in the SLT.
GFC VPI
0 0 0 0 0 0 0 1 1 1 1 11 0 0
Pointer1
(If in multi-PHY UTOPIA master mode)
VCI
0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0
Pointer2

39.1.2.4 Preventing Channel Aliasing

Reliable one-to-one mapping of VCs to local channel numbers requires that the address bits
not taken into account during the translation have a fixed value (chosen to be zero).
Otherwise, multiple VCs could translate to a single local channel number. The CUMB
feature (check unused mask bits) can be used to test the reliability of the mapping by
screening out misinserted cells. When FLMASK[CUMB] is set, address header bits not
used in the first- and second-level address masking procedure are checked for non-zero
values. If a non-zero value is found, the cell is passed to the global raw cell queue. See
Table 38-11 for a description of the CUMB bit.
PTI
FLBASE
FLMASK
PHY#
SLBASE
Figure 39-2. Address Compression
MPC850 Family User's Manual
First-level addressing table (FLT)
32-bit entries
SLMASK
Second-level addressing tables (SLTs)
16-bit entries
ch#
64 Kbyte
memory space
SLTOFFSET