Memory Controller And External Bus Clocks (Gclk1_50 Gclk2_50, Clkout) - Freescale Semiconductor MPC850 User Manual

The high frequency is generated by using the DFNH field in the SCCR and it is used in
normal high and doze high mode. The low frequency is generated using the DFNL field in
the SCCR and it is used in normal low and doze low mode. The DFNH and DFNL dividers
are cleared by HRESET, and therefore GCLKx defaults to VCOOUT.
The frequency for the GCLKx system clock is:
VCOOUT
GCLKx = --------------------------------------------------------------
freq
DFNH
( 2 )or 2
When GCLKx is divided, its duty-cycle is modified. One phase remains the same while the
other stretches out. GCLKx no longer has a 50% duty cycle when the division factor is
greater than 1, as shown in Figure 14-7.
GCLK1 Divided by 1
GCLK2 Divided by 1
GCLK1 Divided by 2
GCLK2 Divided by 2
GCLK1 Divided by 4
GCLK2 Divided by 4
Figure 14-7. Divided System Clocks (GCLKx) Timing Diagram
14.3.1.2 Memory Controller and External Bus Clocks (GCLK1_50,
GCLK2_50, CLKOUT)
The MPC850 provides the capability to run the external bus and memory controller at a
lower frequency than the internal modules. This capability is provided by the external bus
frequency dividers. The external bus clocks GCLK1_50 and GCLK2_50 are derived from
GCLK1 and GCLK2, as determined by the SCCR[EBDF]. SCCR[EBDF] is cleared by
HRESET, and thus GCLK1_50 and GCLK2_50 default to GCLK1 and GCLK2. The
timing relationship between GCLKx and GCLKx_50 is shown in Figure 14-8.
freq
DFNL 1 +
( )
Chapter 14. Clocks and Power Control
Clock Signals