Sar Receive State Register (Srstate) - Freescale Semiconductor MPC850 User Manual

SAR Receive State Register (SRSTATE)

38.2 SAR Receive State Register (SRSTATE)
The SAR receive state register (SRSTATE), shown in Figure 38-2, contains user-initialized
global state parameters.
BIT
FIELD
RESET
OPER
Figure 38-2. SAR Receive State Register (SRSTATE)
The SRSTATE fields are described in Table 38-4.
Bits Name
EXT
0 Extended channel mode. EXT and ACP select the address matching mechanism; see Section 38.5,
"Address Match Parameters (AM1–AM5)."
0 Maximum of 31.5 channels available. (Receive channel 0 is reserved for the raw cell queue.)
Channel mapping and connection tables are supported internally. Internal look-up table channel
mapping mechanism is used.
1 Maximum of 65534.5 channels available. (Channel 65535 and receive channel 0 are reserved.)
Channel mapping and connection tables are supported externally. CAM or address compression is
used for channel mapping.
ACP
1 Address compression. Valid only if EXT = 1. EXT and ACP select the address matching mechanism;
see Section 38.5, "Address Match Parameters (AM1–AM5)."
0 CAM is used for channel mapping.
1 Address compression mechanism is used for channel mapping.
EC
2 Expanded cell. This option is valid only in UTOPIA mode.
0 Standard 53-byte ATM cell is used.
1 Expanded cells are used on all ATM cells. Cell length can be bytes, as defined by ECSIZE in the
parameter RAM.
3 SNC Synchronization status. Valid only in UTOPIA mode (PDPAR[UT] =1).
0 SOC sync is lost. Also reported via an interrupt in the UTOPIA event register (IDSR1[SYNC]).
1 SOC is in sync.
Should be cleared during initialization.
4 Reserved
—
DIS
5 Disable. Used to disable all receive processes in UTOPIA mode. This function is used only when
initializing the UTOPIA port. It must not be written to while the UTOPIA port is operating.
0 Receive enabled.
1 Receive disabled.
SER
6 ATM physical interface type
0 UTOPIA PHY
1 Serial PHY
MPHY Multiple PHY operation. Valid only in UTOPIA mode.
7
0 Single PHY mode
1 Multiple PHY mode
0 1 2
EXT ACP EC
— — —
R/W R/W R/W
Table 38-4. SRSTATE Field Descriptions
MPC850 Family User's Manual
3 4 5
SNC DIS
—
— — —
R/W R/W R/W
Description
6 7
SER MPHY
— —
R/W R/W