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25.9.1 General SCC Mode Register (GSMR)
Table 25-2 shows asynchronous HDLC-specific information for the GSMR.
Table 25-2. Asynchronous HDLC-Specific GSMR Field Descriptions
Name
RFW
Rx FIFO width (GSMR_H[26])
0 Do not use.
1 Low-latency operation—for character-oriented protocols like UART, BISYNC, and asynchronous HDLC.
The Rx FIFO is 8 bits wide and the Rx FIFO is one-fourth its normal size (8 bytes for SCC2; 4 bytes for
SCC3). This allows each character to be written to the buffer without waiting for 32 bits to be received.
TDCR/
Tx/Rx divide clock rate (GSMR_L[14–15/16–17]). For asynchronous HDLC mode, 8×, 16×, or 32× must be
RDCR
chosen. Set TDCR = RDCR in most applications.
00 Do not use.
01 8× clock mode (do not use for IrLAP).
10 16× clock mode.
11 32× clock mode (do not use for IrLAP).
25.9.2 Data Synchronization Register (DSR)
The data synchronization register (DSR) is reserved in asynchronous HDLC mode. It
should be left in its reset state of 0x7E7E.
25.10 Programming the Asynchronous HDLC
Controller
Asynchronous HDLC mode is selected for an SCC by writing GSMR_L[MODE] =
0b0110. The asynchronous HDLC controller uses the same buffer and BD data structure as
other modes and supports multibuffer operation. Receive errors are reported through the
RxBD; transmit errors are reported through the TxBD. Status line information (CD and
CTS) is reported through the port C pins; a maskable interrupt is generated when the status
of either line changes.
25.11 Asynchronous HDLC Commands
The transmit and receive commands are issued to the CP command register (CPCR).
Transmit commands are described in Table 25-3. After a hardware or software reset and a
channel is enabled in the GSMR, the transmitter starts polling the first BD in the TxBD
table every 8 transmit clocks, or immediately if TODR[TOD] = 1, and begins sending data
if TxBD[R] is set.
Chapter 25. SCC Asynchronous HDLC Mode and IrDA
Programming the Asynchronous HDLC Controller
Description
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