Operand Conventions; Data Organization In Memory And Data Transfers; Aligned And Misaligned Accesses - Freescale Semiconductor MPC850 User Manual

Chapter 5
MPC850 Instruction Set
This chapter describes the PowerPC instructions implemented by the MPC850. These
instructions are organized by the level of architecture in which they are
implemented—UISA, VEA, and OEA. These levels are described in Section 3.2.1, "Levels
of the PowerPC Architecture."

5.1 Operand Conventions

This section describes the operand conventions as they are represented in two levels of the
PowerPC architecture. It also provides detailed descriptions of conventions used for storing
values in registers and memory, accessing the MPC850's registers, and representation of
data in these registers.

5.1.1 Data Organization in Memory and Data Transfers

Bytes in memory are numbered consecutively starting with 0. Each number is the address
of the corresponding byte.
Memory operands may be bytes, half words, words, or double words, or, for the load/store
multiple and move assist instructions, a sequence of bytes or words. The address of a
memory operand is the address of its first byte (that is, of its lowest-numbered byte).

5.1.2 Aligned and Misaligned Accesses

The operand of a single-register memory access instruction has a natural alignment
boundary equal to the operand length. In other words, the natural address of an operand is
an integral multiple of the operand length. A memory operand is said to be aligned if it is
aligned at its natural boundary; otherwise it is misaligned.
Operands for single-register memory access instructions have the characteristics shown in
Table 5-1 (Although not permitted as memory operands, quad words are shown because
quad-word alignment is desirable for certain memory operands.).
Chapter 5. MPC850 Instruction Set