Smc Mode Registers (Smcmrn) - Freescale Semiconductor MPC850 User Manual

• Two SMCs support the two sets of C/I and monitor channels in the SCIT channels 0
and 1
• Full-duplex operation
• Local loopback and echo capability for testing
30.2 Common SMC Settings and Configurations
The following sections describe settings and configurations that are common to the serial
management controllers.

30.2.1 SMC Mode Registers (SMCMRn)

The two SMC mode registers (SMCMR), shown in Figure 30-2, select the SMC mode as
well as mode-specific parameters. The functions of SMCMR[8–15] are the same for each
protocol. SMCMR[0–7] vary according to the protocol selected by SMCMR[SM].
Bit 0 1
Field: UART —
Transparent
GCI
Reset
R/W
Address
Table 30-1 describes SMCMR fields.
Bits Name
0 — Reserved, should be cleared
2 3 4 5
CLEN SL PEN
— BS
ME
0xA82 (SMCMR1), 0xA92 (SMCMR2)
Figure 30-2. SMC Mode Registers (SMCMRn)
Table 30-1. SMCMR Field Descriptions
Chapter 30. Serial Management Controllers (SMCs)
Common SMC Settings and Configurations
6 7 8 9
PM —
REVD
— C#
0
R/W
Description
10 11 12 13 14
SM DM TEN REN
15