Register Lock Mechanism - Freescale Semiconductor MPC850 User Manual

Mpc850 family integrated communications microprocessor
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Programming the SIU
Table 10-5. TESR Field Descriptions (Continued)
Bits
Name
26
DEXT
Data external transfer error acknowledge. Set if the cycle is terminated by an externally generated
TEA signal when a data load or store is requested by an internal master.
27
DTMT
Data transfer monitor timeout. Set if the cycle is terminated by a bus monitor timeout when a data
load or store is requested by an internal master.
28–31
DPB[0–3] Data parity error on bytes 0–3. Each byte lane has four parity error status bits; one is set for the
byte that had a parity error when an internal master requested a data load. Parity checking for
memory not controlled by the memory controller is enabled by SIUMCR[PNCS], see Table 10-3.

10.4.5 Register Lock Mechanism

If the MPC850 sets PLPRCR[LPM] = 11 before entering power-down mode, then the
registers of the SIU maintained by KAPWR are automatically protected. However, to
provide protection of the SIU registers maintained by KAPWR against uncontrolled
shutdown, a register locking mechanism is included. These registers can be write-protected
in a set of associated key registers. The MPC850 key registers are shown in Table 10-6.
Offset
0x300
0x304
0x308
0x30C
0x310–31F Reserved
0x320
0x324
0x328
0x32C
0x330–33F Reserved
0x340
0x344
0x348–37F Reserved
0x380
0x384
0x388
0x38C–7F
F
Table 10-6. Key Registers
System Integration Timers Keys
TBSCRK—Timebase status and control register key
TBREFAK—Timebase reference register A key
TBREFBK—Timebase reference register B key
TBK—Timebase/decrementer register key
RTCSCK—Real-time clock status and control register key
RTCK—Real-time clock register key
RTSECK—Real-time alarm seconds key
RTCALK—Real-time alarm register key
PISCRK—Periodic interrupt status and control register key
PITCK—Periodic interrupt count register key
Clocks and Reset Keys
SCCRK—System clock control key
PLPRCRK—PLL, low power and reset control register key
RSRK—Reset status register key
Reserved
MPC850 Family User's Manual
Description
Name
Size
32 bits
32 bits
32 bits
32 bits
16 bytes
32 bits
32 bits
32 bits
32 bits
16 bytes
32 bits
32 bits
56 bytes
32 bits
32 bits
32 bits
1140 bytes

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