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Watchpoints and Breakpoints Support
exception routine. Therefore, the value of the counter inside the breakpoint exception
routine equals zero.
44.2.3.4 Trap Enable Programming
The trap enable bits can be programmed by regular software (only if MSR[PR] = 0) using
the mtspr instruction or on-the-fly using the special development port interface. See
Section 44.3.2.4, "Development Port Serial Communications–Trap Enable Mode." The
value used by the breakpoint generation logic is the bit-wise OR of the software trap enable
bits written using the mtspr instruction, and the development port trap enable bits that are
serially shifted using the development port. The software trap enable bits and development
port trap enable bits can be read from ICTRL and the LCTRL2 using the mtspr instruction.
Table 44-20 and Table 44-22 show the exact bit placement.
44.2.4 Operation Details
The following sections describe various operating details of watchpoint and breakpoint.
44.2.4.1 Restrictions
The same watchpoint can be detected more than once during execution of an instruction.
For example, a load/store watchpoint can be detected on more than one transfer when
executing load/store multiple/string instructions or a load/store watchpoint can be detected
on more than one byte in byte mode. In such cases only one watchpoint of a given type is
reported for the instruction. Similarly, only one watchpoint of the same type can be counted
for a single instruction. Watchpoint events are reported when the instruction that caused the
event retires; because more than one instruction can retire in a single clock, ensuing events
may be reported in the same clock. Moreover, an event detected on more than one
instruction (tight loops or range detection) can only be reported once. Internal counters
count correctly in these cases.
44.2.4.2 Byte and Half Word Working Modes
The user can use watchpoints and breakpoints to detect matches on bytes and half words
when the byte/half word is accessed in a load/store instruction of larger data widths. For
example, when loading a table of bytes using a series of load word instructions.) To use this
feature in word mode, write the required match value to the correct half word of the data
comparator and the mask in the L-data comparator. To break on bytes, the byte mask for
each L-comparator and the bytes to be matched must be written in the data comparator.
Because bytes and half words can be accessed using a larger data width instruction, the user
cannot predict the exact value of the L-address lines when the requested byte/half-word is
accessed. If the matched byte is byte 2 of the word and accessed using a load word
instruction, the L-address value will be of the word (byte 0). Therefore, the core masks the
two lsbs of the L-address comparators for word accesses and the lsb for half-word accesses.
Address range is supported only when aligned according to access size.
Chapter 44. System Development and Debugging
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