Encoding Data With A Dpll - Freescale Semiconductor MPC850 User Manual

Decoding Method
NRZI Mark
NRZI Space
FM0
FM1
Manchester
Differential Manchester
The DPLL can also be used to invert the data stream of a transfer. This feature is available
in all encodings, including standard NRZ format. Also, when the transmitter is idling, the
DPLL can either force TXD high or continue encoding the data supplied to it.
The DPLL is used for UART encoding/decoding, which gives the option of selecting the
divide ratio in the UART decoding process (8×, 16×, or 32×). Typically, 16× is used.
The maximum data rate supported with the DPLL is 3.125 MHz, assuming a 25-MHz
system clock and the 8× ratio (25 MHz/8 = 3.125 MHz). Thus, the frequency applied to
CLKx or generated by an internal baud rate generator may be up to 25 MHz on a 25-MHz
MPC850, if the DPLL 8×, 16×, or 32× option is used.
Note the 1:2 system clock/serial clock ratio does not apply when the DPLL is used to
recover the clock in the 8×, 16×, or 32× modes. Synchronization occurs internally after the
DPLL generates the Rx clock. Therefore, even the fastest DPLL clock generation (the 8×
option) easily meets the required 1:2 ratio clocking limit.

21.4.5.1 Encoding Data with a DPLL

Each SCC contains a DPLL unit that can be programmed to encode and decode the SCC
data as NRZ, NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential
Manchester. Figure 21-15. shows the different encoding methods.
Table 21-7. Preamble Requirements
Preamble Pattern
All zeros
All ones
All ones
All zeros
101010...10
All ones
Chapter 21. Serial Communications Controllers
SCC Parameter RAM
Minimum Preamble Length Required
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit