Load/Store Instruction Timing - Freescale Semiconductor MPC850 User Manual

Table 9-1. Instruction Execution Timing (Continued)
Instructions
Move to/from SPR (Debug, DAR, DSISR): mtspr, mfspr
String instructions: lswi, lswx, stswi, stswx. See
Section 9.2.2, "String Instruction Latency."
Memory control instructions: isync
Order memory access: eieio
Cache control: icbi
1
Although a store (as well as mtspr for SPRs external to the core) issued to the LSU buffer frees the core
pipeline, the next load or store is not performed on the bus until it is free.
2
See Table 4-5.
3
Refer to Chapter 4, "PowerPC Core Register Set."
4
See Section 4.1.1.1.1, "Condition Register (CR)," and Section 4.1.2.3.1, "Machine State Register (MSR)."
5
DivisionLatency
6
Division blockage = division latency
7
Blockage of the multiply instruction is dependent on the next instruction.If the next instruction is a divide, the
blockage is 2 clocks; otherwise, the blockage is 1 clock.
8
Assumes nonspeculative aligned access, on-chip memory, and available bus. See Section 3.6.3.4,
"Nonspeculative Load Instructions," Section 3.6.3.5, "Unaligned Accesses," and Section 9.2.1, "Load/Store
Instruction Timing."

9.2.1 Load/Store Instruction Timing

Table 9-2. summarizes load/store instruction timings. This table assumes zero wait-state
memory references on a parked bus and pipelined external memory accesses.
Instruction Type
Integer single target register load (aligned)
Integer single target register store (aligned)
Load/store multiple
1
N denotes the number of registers transferred.
–
34 divisorLength

NoOverflow ⇒ 3 + ------------------------------------------------------

=
----------------------------------------------------------------------------------------------------------------------- -
Table 9-2. Load/Store Instructions Timing
Cache
2 cycles
1 cycle
1 + N
Chapter 9. Instruction Execution Timing
Latency Blockage
Serialize + 1
Serialize + 1 + no. of words
accessed
Serialize
1
1
Where
Overflow


4
Latency
Data External
Memory
5 cycles
1 cycle
1
N 1 +
 
3 N + +
--------------
 
3
Instruction Timing List
Unit Serializing
LSU Yes
LSU Yes
BPU Yes
LSU Next load/store
is synchronized
with ones
before
LSU, No
I-cache
  or MaxNegativeNumber x

=
-- -   -------------------------------------------------------------- -

0 1 –
Cleared from LSU
Data External
Cache Memory
2 cycles 5 cycles
2 cycles 5 cycles
1 + N
N 1 +

3 N + +
--------------

3



