I2C Features - Freescale Semiconductor MPC850 User Manual

I2C Features

The I 2 C receiver and transmitter are double-buffered, which corresponds to an effective
two-character FIFO latency. In normal operation, the msb (bit 0) is shifted out first. When
the I 2 C is not enabled in the I
33.1 I C Features
2
The following is a list of the I
• Two-signal interface (SDA on PB[27] and SCL on PB[26])
• Support for master and slave I
• Multiple-master environment support
• Continuous transfer mode for autoscanning of a peripheral
• Supports a maximum clock rate of 520 KHz (with a CPM utilization of 25%),
assuming a 25-MHz system clock.
• Independent, programmable baud-rate generator
• Supports 7-bit I
• Open-drain output signals allow multiple master configuration
• Local loopback capability for testing
33.2 I C Controller Clocking and Signal Functions
2
2
The I C controller can be configured as a master or slave for the serial channel. As a master,
the controller's BRG provides the transfer clock. The I
clock (BRGCLK), which is described in Section 14.3, "Clock Signals."
SDA and SCL are bidirectional signals connected to a positive supply voltage through an
external pull-up resistor. When the bus is free, both signals are pulled high. The general I
master/slave configuration is shown in Figure 33-2.
Figure 33-2. I
When the I 2 C controller is the master, the SCL clock output, taken directly from the I
BRG, shifts receive data in and transmit data out through SDA. The transmitter arbitrates
for the bus during transmission and aborts if it loses arbitration. When the I
a slave, the SCL clock input shifts data in and out through SDA. The SCL frequency can
range from DC to BRGCLK/48.
2 C mode register (I2MOD[EN] = 0), it consumes little power.
2 C controller's main features:
2 C operation
2
C addressing
Master
SCL
SDA
2
C Master/Slave General Configuration
MPC850 Family User's Manual
2
C BRG takes its input from the BRG
V DD
SCL
(EEPROM, for example)
SDA
V DD
Slave
2 C controller is
2
C
2 C