Timer Mode Registers (Tmr1–Tmr4) - Freescale Semiconductor MPC850 User Manual

Table 17-1. TGCR Field Descriptions (Continued)
Bits Name
8 CAS2 Cascade timers.
0 Normal operation.
1 Timers 1 and 2 are cascaded to form a 32-bit timer.
GM1
12 Gate mode for TGATE1. Valid only if TMR1[GE] or TMR2[GE] is set.
0 Restart gate mode. A falling TGATE1 enables and restarts the count and a rising edge of TGATE1
disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not restart
the count value in the TCN.
17.2.4 Timer Mode Registers (TMR1–TMR4)
The timer mode registers (TMR1–TMR4), shown in Figure 17-6, are identical. Before
modifying TMRx, reset the timer by clearing TGCR[RSTx].
Bit 0 1 2
Field
Reset
R/W
Addr
Figure 17-6. Timer Mode Registers (TMR1–TMR4)
Table 17-2 describes the TMR fields.
Bits Name
PS
0–7 Prescaler value. The prescaler is programmed to divide the clock input by a value between 1 and
256. A 0x00 value divides the clock by 1; 0xFF divides it by 256.
8–9 CE Capture edge and enable Interrupt.
00 Disable interrupt on capture event; capture function is disabled.
01 Capture on rising TINx edge only and enable interrupt on capture event.
10 Capture on falling TINx edge only and enable interrupt on capture event.
11 Capture on any TINx edge and enable interrupt on capture event.
OM
10 Output mode. Valid for timers 1 and 2 only.
0 Active-low pulse on TOUTx for one timer input clock cycle as defined by ICLK. Thus, TOUTx may
be low for one general system clock period, one general system clock/16 period, or one TINx
clock cycle period. Changes to TOUTx occur on the falling edge of the system clock.
1 Toggle TOUTx. Changes to TOUTx occur on the falling edge of the system clock.
ORI
11 Output reference interrupt enable.
0 Disable interrupt for reference that is reached. Does not affect an interrupt on the capture function.
1 Enable interrupt when the reference value is reached.
FRR
12 Free run/restart.
0 Free run. The timer count continues to increment after the reference value is reached.
1 Restart. The timer count is reset immediately after the reference value is reached.
3 4 5 6
PS
0x990 (TMR1), 0x992 (TMR2), 0x9A0 (TMR3), 0x9A2 (TMR4)
Table 17-2. TMR1–TMR4 Field Descriptions
Chapter 17. Communications Processor Module and CPM Timer
CPM General-Purpose Timers
Description
7 8 9 10
CE OM ORI
0
R/W
Description
11 12 13 14
FRR ICLK
15
GE