B.1 Serial Clocking (Peak Rate Limitation) - Freescale Semiconductor MPC850 User Manual

Appendix B
Serial Communications Performance
Due to the architecture of the MPC850, the overall performance of the serial channels
cannot be stated in absolute terms. The serial channels of the MPC850 can be programmed
in many different modes, which require different degrees of processing. There may be
several individual bottlenecks in the system, with their own specific considerations. These
are described in the following sections.

B.1 Serial Clocking (Peak Rate Limitation)

The maximum rate at which a serial channel can be clocked is governed by the
synchronization hardware of the serial channels. The rate at which the serial channel can be
clocked depends on the physical interface of the channel. Examples include:
• maximum clocking rate for an SCC connected to a dedicated set of pins (NMSI
mode)=SYNCCLK/2
• maximum clocking rate for the TDM channel=SYNCCLK/2.5
For limitations of other channels, refer to the appropriate chapter of the manual.
SYNCCLK is a programmable clock rate which is derived from the system frequency; see
Chapter 14, "Clocks and Power Control." At its maximum rate, it is equal to the system
frequency.
The maximum serial clock rate is a limitation on the peak data rate. This is the maximum
rate at which the receiver or transmitter hardware can transfer data between its internal
FIFO and the serial line. However, this rate is higher than the rate at which data in these
internal FIFOs can be processed by the CPM and transferred to system memory. Therefore,
this peak rate can only be maintained for short bursts which do not exceed the internal FIFO
depth. The serial clocks must also be turned off between these bursts. The FIFOs of the
SCCs are 32 bytes for SCC2 and 16 bytes for SCC3[2–4]. The SMCs and SPI are
double-buffered, and thus have an effective FIFO depth of two characters. The USB FIFOs
are 16 bytes.
Appendix B. Serial Communications Performance