C.2 Powerpc Registers—Supervisor Registers - Freescale Semiconductor MPC850 User Manual

PowerPC Registers—Supervisor Registers
C.2 PowerPC Registers—Supervisor Registers
All supervisor-level registers implemented on the
register (MSR), described in Table C-3
Table C-3. Supervisor-Level PowerPC Registers
Description
Machine state
register
Table C-4 lists supervisor-level SPRs defined by the PowerPC architecture.
SPR Number
Decimal SPR[5–9] SPR[0–4]
18 00000
19 00000
22 00000
26 00000
27 00000
272 01000
273 01000
274 01000
275 01000
284 01000
285 01000
287 01000
1
Any read (mftb) to this address causes an implementation-dependent software emulation exception.
.
Name
MSR See Section 4.1.2.3.1, "Machine State Register
(MSR)."
Table C-4. Supervisor-Level PowerPC SPRs
Name
10010 DSISR See the Programming Environments
Manual and Section 4.1.2.1, "DAR,
DSISR, and BAR Operation."
See the Programming Environments
10011 DAR
Manual and Section 4.1.2.1, "DAR,
DSISR, and BAR Operation."
10110 DEC See Section 10.8.1, "Decrementer
Register (DEC)," and in Chapter 14,
"Clocks and Power Control"
11010 SRR0 See SRR0 settings for individual
exceptions in Chapter 6,
"Exceptions."
11011 SRR1 See SRR1 settings for individual
exceptions in Chapter 6,
"Exceptions."
10000 SPRG0 See the Programming Environments
Manual.
10001 SPRG1
10010 SPRG2
10011 SPRG3
11100 TBL See Section 10.9, "The PowerPC
1
write Timebase
and Power Control."
11101 TBU
1
write
11111 PVR Section 4.1.2.3.2, "Processor Version
Register."
MPC850 Family User's Manual
MPC850
are SPRs, except for the machine state
Comments
Comments
,"
and Chapter 14, "Clocks
Serialize Access
Write fetch sync
Serialize Access
Write: Full sync
Read: Sync relative to
load/store operations
Write: Full sync
Read: Sync relative to
load/store operations
Write
Write
Write
Write
Write (as a store)
No (read-only register)