Idma Registers; Dma Channel Mode Registers (Dcmr) - Freescale Semiconductor MPC850 User Manual

Table 19-4. IDMA Parameter RAM Memory Map (Continued)
0x0C IBPTR
0x0E WRITE_SP
0x10 S_BYTE_C
0x14 D_BYTE_C
0x18 S_STATE
0x1C ITEMP
0x2C SR_MEM
0x30 READ_SP
0x32 —
0x34 —
0x36 —
0x38 D_STATE
• Notes: Boldfaced items must be initialized by the user before enabling an IDMA channel. The remaining
parameters are used by the CP only.
1
IDMA1 base = IMMR + 0x3CC0
IDMA2 base = IMMR + 0x3DC0

19.3.3 IDMA Registers

Each IDMA channel has a DMA channel mode register (DCMR), an IDMA status register
(IDSR) and corresponding mask register (IDMR) that contain global channel parameters.

19.3.3.1 DMA Channel Mode Registers (DCMR)

Located in each IDMA's parameter RAM, the DMA channel mode registers (DCMR)
configure the peripheral port size, the source and destination type of the transfer, and the
address mode (cycle mode) of the IDMA channels. Figure 19-5 shows the register format.
Bit 0 1
Field
Reset
R/W
Addr
Figure 19-5. DMA Channel Mode Register (DCMR)
Hword Current IDMA BD pointer. If the IDMA channel is idle, IBPTR points to the next
valid BD in the table. After a reset, or when the end (wrap bit) of the BD table is
reached, the CP wraps IBPTR back to IBASE.
Hword Internal-use
Word Internal source byte count
Word Internal destination byte count
Word Internal state
4 Words Temp data storage
Word Data storage for peripheral write
Hword Internal-use
Hword Difference between source and destination residue
Hword Temp storage address pointer
Hword SR_MEM byte count
Word Reserved. Internal state used by CP
2 3 4 5
—
0
R
Chapter 19. SDMA Channels and IDMA Emulation
6 7 8 9
IDMAx Base + 0x02
IDMA Emulation
10 11 12 13
SIZE S/D
0 0
R/W R/W
14 15
SC
0
R/W