Alignment And Data Packing On Transfers - Freescale Semiconductor MPC850 User Manual

CLKOUT
BR
BG
BB
A[6–27]
A[28–29]
A[30–31]
R/W
TSIZ[0–1]
BURST
TS
BDIP
Data
TA
BI
Figure 13-18. Burst-Inhibit Cycle: 32-Bit Port Size

13.4.5 Alignment and Data Packing on Transfers

The MPC850 external bus supports only natural address alignment:
• Byte access can have any address alignment.
• Half-word access must have A[31] = 0b0.
• Word access must have A[30–31] = 0b00.
• For burst accesses A[30–31] = 0b00.
n n+1 Mod 4
00
Chapter 13. External Bus Interface
n+2 Mod 4 n+3 Mod 4
Bus Operations