Asynchronous Hdlc Channel Implementation; Asynchronous Hdlc Mode Parameter Ram - Freescale Semiconductor MPC850 User Manual

25.7 Asynchronous HDLC Channel Implementation

The following points are specific to asynchronous HDLC channel implementation:
• Flag sequence—The transmitter automatically generates the opening and closing
flags. The receiver removes opening and closing flags before writing a frame to
memory and receives frames with only one shared flag between frames, ignoring
multiple flags.
• Address field—The address field is neither generated nor examined by the
microcode while sending or receiving. The destination address field of the frame
must be included in the Tx buffer. Any address field compression, expansion, or
checking must be performed by the core.
• Control field—The control field is neither generated nor examined by the microcode
during a transfer. The control field of the frame must be included in the buffer. Any
control field compression, expansion, or checking is done by the core.
• Frame check sequence—When sending, the frame check sequence (FCS) is
appended to the frame before the closing flag is sent. The FCS is generated on the
original frame before transparency characters, start/stop bits, or flags are added.
When receiving, the FCS is checked automatically and calculated after any
transparency characters, start/stop bits, and flags are removed. For both, the
controller uses only a 16-bit CRC-CCITT polynomial.
• Encoding—The asynchronous HDLC controller supports 8 data bits, one start bit,
one stop bit, and no parity. Program PSMR[CHLN] to 0b11 for proper operation.
• Idle characters—When sending, the asynchronous HDLC controller sends idle
characters when no data is available; when receiving, it ignores idle characters.

25.8 Asynchronous HDLC Mode Parameter RAM

For asynchronous HDLC mode, the protocol-specific area of the SCC parameter RAM is
mapped as in Table 25-1.
Table 25-1. Asynchronous HDLC-Specific SCC Parameter RAM
1
Offset Name
0x30 —
0x34 C_MASK
C_PRES
0x38
BOF
0x3C
EOF
0x3E
ESC
0x40
0x42 —
ZERO
0x46
Memory Map
Width
Word Reserved
Word CRC constant. Initialize with 0x0000_F0B8.
Word CRC preset. Initialize with 0x0000_FFFF.
Hword Beginning-of-flag-character. Initialize to PPP-0x7E, IrLAP - 0xC0.
Hword End-of-flag character. Initialize to PPP-0x7E, IrLAP-0xC1.
Hword Control escape character. Initialize to 0x7D for both PPP and IrLAP.
Word Reserved
Hword Clear this field.
Chapter 25. SCC Asynchronous HDLC Mode and IrDA
Asynchronous HDLC Channel Implementation
Description