Burst Operations - Freescale Semiconductor MPC850 User Manual

Bus Operations
support bursting. For this type of cycle, the selected slave device supplies/samples the
address of the first word of the asserts the burst-inhibit signal (BI) with TA for the first
transfer of the burst access. The MPC850 responds by terminating the burst and accessing
the rest of the 16-byte block, using three read/write cycles (each one for a word) for a 32-bit
port-width slave, seven read/write cycles for a 16-bit port-width slave, or fifteen read/write
cycles for a 8-bit port-width slave.
The general case of burst transfers assumes that external memory has a 32-bit port size. The
MPC850 provides an effective mechanism for interfacing with 16-bit port size memories
and 8-bit port size memories allowing burst transfers to these devices when they are
controlled by the internal memory controller. In this case, the MPC850 attempts to initiate
a burst transfer as in the normal case. If, in a cycle before the TA is asserted for the first
beat, the memory controller responds that the port size is 16-/8-bits and that the burst is
accepted, the MPC850 completes a 8-/16-beat burst. Each data beat effectively transfers
only 2/1 bytes. Note that this 8-/16-beat burst is considered an atomic transaction, so the
MPC850 will not allow other unrelated master accesses or bus arbitration between
transfers.

13.4.4 Burst Operations

The MPC850 burst mechanism uses additional signals to the basic protocol: BURST
indicates that the cycle is a burst cycle, burst data in progress (BDIP) indicates the duration
of the burst data, and burst inhibit (BI) indicates whether the slave supports bursts. Along
with asserting TS, the master drives the address, address attributes, and BURST signals to
indicate that a burst transfer is being initiated. Slaves that support bursting negate BI. If the
slave cannot burst, it asserts BI. During the data phase of a burst write cycle the master
drives the data. The master also asserts BDIP if it intends to drive the data beat after the
current one.
When the slave has received the data, it asserts TA to indicate to the master that it is ready
for the next transfer. The master again drives the next data and asserts or negates BDIP. If
the master does not intend to drive another data beat, it negates BDIP to indicate to the slave
that the next data beat is the last one in the burst write.
Bursts performed by MPC850 internal masters are always 16 bytes. The MPC850 memory
controller responds only to fixed-length bursts (also typically programmed to be 16 bytes).
Therefore, devices in an MPC850 system should attempt only 16-byte burst transfers
except for external masters with a dedicated chip select, such as an external MPC603 that
bursts to a chip select programmed for a 32-byte burst.
During the data phase of a burst read cycle, the master receives data from the addressed
slave. If the master needs more than one data, it asserts BDIP. When the master receives the
next-to-last data, it negates BDIP. Thus, the slave stops driving new data after receiving the
negation of BDIP at the rising clock edge.
MPC850 Family User's Manual