Freescale Semiconductor MPC850SR Manuals

Manuals and User Guides for Freescale Semiconductor MPC850SR. We have 1 Freescale Semiconductor MPC850SR manual available for free PDF download: User Manual

Freescale Semiconductor MPC850SR User Manual (1178 pages)

MPC850 Family Integrated Communications Microprocessor

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 12 MB

Overview

7
- Table of Contents
  7
Section 2

41
- Chapter 16 System Configuration
  
  42
Section 3

47
- About this Book
  67
- Appendix C
  
  69
- Appendix D
  
  69
- Appendix E
  
  69
  - Serial Interface
    69
    
    SCC UART Mode
    70
    
    Acronyms and Abbreviations
    74
    
    Intended Audience
    79
    
    Features
    84
    
    Overview of Major Components
    89
  - Chapter 1 Powerpc Microprocessor Module
    
    90
    
    System Interface Unit (SIU)
    90
    
    Resets
    91
    
    MPC850 Hardware Interface
    92
    
    Signals
    93
    
    Clocking and Power Management
    95
  - Chapter 15 Memory Controller
    
    96
    
    Communications Processor Module (CPM)
    97
    
    Differences between the MPC850 Family and MPC860
    99
    
    System Debugging and Testing Support
    99
  - Chapter 2 Memory Map
    
    101
  - Chapter 3
    
    117
    
    Powerpc Architecture Overview
    117
    
    The MPC850 Core as a Powerpc Implementation
    117
    
    Levels of the Powerpc Architecture
    119
    
    Features
    120
    
    Basic Structure of the Core
    121
    
    Instruction Flow
    122
    
    Basic Instruction Pipeline
    123
    
    Branch Operations
    123
    
    Instruction Unit
    123
    
    Dispatching Instructions
    125
    
    Execution Units
    125
    
    Register Set
    125
    
    Branch Processing Unit
    126
    
    Integer Unit
    126
    
    Load/Store Unit
    126
    
    Executing Load/Store Instructions
    128
    
    Serializing Load/Store Instructions
    128
    
    Store Accesses
    128
    
    Nonspeculative Load Instructions
    129
    
    Unaligned Accesses
    129
    
    Atomic Update Primitives
    130
    
    The MPC850 and the Powerpc Architecture
    130
    
    MPC850 Register Implementation
    135
    
    Powerpc Registers—User Registers
    136
  - Chapter 4 Powerpc User-Level Register Bit Assignments
    
    136
    
    Condition Register (CR)
    136
    
    Powerpc Registers—Supervisor Registers
    138
    
    Time Base Registers
    138
    
    DAR, DSISR, and BAR Operation
    139
    
    Machine State Register (MSR)
    140
    
    Powerpc Supervisor-Level Register Bit Assignments
    140
    
    Unsupported Registers
    140
    
    Processor Version Register
    142
    
    Accessing Sprs
    145
    
    Register Initialization at Reset
    145
    
    Operand Conventions
    147
  - Chapter 5
    
    147
    
    Aligned and Misaligned Accesses
    147
    
    Data Organization in Memory and Data Transfers
    147
    
    Instruction Set Summary
    148
    
    Classes of Instructions
    149
    
    Illegal Instruction Class
    150
    
    Addressing Modes
    151
    
    Memory Addressing
    151
    
    Reserved Instruction Class
    151
    
    Context Synchronization
    152
    
    Effective Address Calculation
    152
    
    Synchronization
    152
    
    Execution Synchronization
    153
    
    Instruction Set Overview
    153
    
    Instruction-Related Exceptions
    153
    
    Integer Arithmetic Instructions
    154
    
    Integer Instructions
    154
    
    Powerpc UISA Instructions
    154
    
    Integer Compare Instructions
    155
    
    Integer Logical Instructions
    156
    
    Integer Rotate and Shift Instructions
    156
    
    Integer Load and Store Address Generation
    157
    
    Load and Store Instructions
    157
    
    Integer Store Instructions
    158
    
    Register Indirect Integer Load Instructions
    158
    
    Integer Load and Store Multiple Instructions
    159
    
    Integer Load and Store with Byte-Reverse Instructions
    159
    
    Branch and Flow Control Instructions
    160
    
    Integer Load and Store String Instructions
    160
    
    Branch Instruction Address Calculation
    161
    
    Branch Instructions
    161
    
    Condition Register Logical Instructions
    162
    
    Trap Instructions
    162
    
    Memory Synchronization Instructions—Uisa
    163
    
    Move To/From Condition Register Instructions
    163
    
    Processor Control Instructions
    163
    
    Powerpc VEA Instructions
    165
    
    Processor Control Instructions
    165
    
    Eieio Behavior
    166
    
    Isync Behavior
    166
    
    Memory Synchronization Instructions—Vea
    166
    
    Memory Control Instructions—Vea
    167
    
    Powerpc OEA Instructions
    167
    
    Move To/From Machine State Register Instructions
    168
    
    Move To/From Special-Purpose Register Instructions
    168
    
    Processor Control Instructions—Oea
    168
    
    System Linkage Instructions
    168
    
    Memory Control Instructions—Oea
    169
    
    Exceptions
    172
  - Chapter 6 Exception Ordering
    
    173
    
    Machine Check Interrupt (0X00200)
    175
    
    System Reset Interrupt (0X00100)
    175
    
    DSI Exception (0X00300)
    176
    
    External Interrupt Exception (0X00500)
    176
    
    ISI Exception (0X00400)
    176
    
    Alignment Exception (0X00600)
    177
    
    Integer Alignment Exceptions
    178
    
    Program Exception (0X00700)
    179
    
    Decrementer Exception (0X00900)
    180
    
    System Call Exception (0X00C00)
    180
    
    Trace Exception (0X00D00)
    181
    
    Floating-Point Assist Exception
    182
    
    Instruction TLB Miss Exception (0X01100)
    182
    
    Software Emulation Exception (0X01000)
    182
    
    Data TLB Miss Exception (0X01200)
    183
    
    Instruction TLB Error Exception (0X01300)
    183
    
    Data TLB Error Exception (0X014000)
    184
    
    Debug Exceptions (0X01C00–0X01F00)
    185
    
    Implementing the Precise Exception Model
    186
    
    Recoverability after an Exception
    187
    
    Exception Latency
    188
    
    Partially Completed Instructions
    190
  - Chapter 7
    
    192
    
    Instruction Cache Organization
    192
    
    Data Cache Organization
    194
    
    Cache Control Registers
    196
    
    Instruction Cache Control Registers
    196
    
    Reading Data and Tags in the Instruction Cache
    198
    
    IC_CST Commands
    199
    
    Instruction Cache Enable/Disable Commands
    199
    
    Instruction Cache Load & Lock Cache Block Command
    199
    
    Instruction Cache Unlock Cache Block Command
    200
    
    Data Cache Control Registers
    201
    
    Instruction Cache Invalidate All Command
    201
    
    Instruction Cache Unlock All Command
    201
    
    Reading Data Cache Tags and Copyback Buffer
    204
    
    DC_CST Commands
    205
    
    Data Cache Enable/Disable Commands
    206
    
    Data Cache Load & Lock Cache Block Command
    206
    
    Data Cache Flush Cache Block Command
    207
    
    Data Cache Invalidate All Command
    207
    
    Data Cache Unlock All Command
    207
    
    Data Cache Unlock Cache Block Command
    207
    
    Data Cache Block Touch (Dcbt) and Data Cache Block Touch for Store (Dcbtst)
    208
    
    Instruction Cache Block Invalidate (Icbi)
    208
    
    Powerpc Cache Control Instructions
    208
    
    Data Cache Block Store (Dcbst)
    209
    
    Data Cache Block Zero (Dcbz)
    209
    
    Data Cache Block Flush (Dcbf)
    210
    
    Data Cache Block Invalidate (Dcbi)
    210
    
    Instruction Cache Operations
    210
    
    Instruction Cache Hit
    212
    
    Instruction Cache Miss
    212
    
    Fetching Instructions from Caching-Inhibited Regions
    213
    
    Instruction Fetching on a Predicted Path
    213
    
    Data Cache Operation
    214
    
    Updating Code and Memory Region Attributes
    214
    
    Data Cache Load Hit
    215
    
    Data Cache Read Miss
    215
    
    Data Cache Store Hit in Write-Back Mode
    216
    
    Data Cache Store Hit in Write-Through Mode
    216
    
    Data Cache Store Miss in Write-Through Mode
    216
    
    Write-Back Mode
    216
    
    Write-Through Mode
    216
    
    Data Accesses to Caching-Inhibited Memory Regions
    217
    
    Data Cache Store Miss in Write-Back Mode
    217
    
    Atomic Memory References
    218
    
    Cache Initialization after Reset
    219
    
    Debug Support
    219
    
    Instruction and Data Cache Operation in Debug Mode
    220
    
    Instruction and Data Cache Operation with a Software Monitor Debugger
    220
    
    Features
    223
  - Chapter 8
    
    224
    
    Powerpc Architecture Compliance
    224
    
    Address Translation
    225
    
    Translation Disabled
    225
    
    Translation Enabled
    225
    
    TLB Operation
    227
    
    Using Access Protection Groups
    228
    
    Protection Resolution Modes
    229
    
    Memory Attributes
    230
    
    Translation Table Structure
    231
    
    Level-One Descriptor
    234
    
    Level-Two Descriptor
    235
    
    Page Size
    236
    
    Programming Model
    236
    
    Immu Control Register (Mi_Ctr)
    237
    
    DMMU Control Register (MD_CTR)
    238
    
    IMMU/DMMU Effective Page Number Register (Mx_Epn)
    239
    
    IMMU Tablewalk Control Register (MI_TWC)
    240
    
    Dmmu Tablewalk Control Register (Md_Twc)
    241
    
    Immu Real Page Number Register (Mi_Rpn)
    242
    
    DMMU Real Page Number Register (MD_RPN)
    243
    
    Mmu Current Address Space ID Register (M_Casid)
    245
    
    Mmu Tablewalk Base Register (M_Twb)
    245
    
    Mmu Access Protection Registers (Mi_Ap/Md_Ap)
    246
    
    MMU Debug Registers
    246
    
    Mmu Tablewalk Special Register (M_Tw)
    246
    
    Immu Cam Entry Read Register (Mi_Cam)
    247
    
    Immu Ram Entry Read Register 0 (Mi_Ram)
    248
    
    Dmmu Cam Entry Read Register (Md_Cam)
    249
    
    Immu Ram Entry Read Register 1 (Mi_Ram)
    249
    
    DMMU RAM Entry Read Register 0 (MD_RAM0)
    250
    
    DMMU RAM Entry Read Register 1 (MD_RAM1)
    251
    
    Memory Management Unit Exceptions
    253
    
    TLB Manipulation
    253
    
    TLB Reload
    254
    
    Translation Reload Examples
    254
    
    Locking TLB Entries
    255
    
    Loading Locked TLB Entries
    256
    
    TLB Invalidation
    256
    
    Instruction Execution Timing Examples
    257
  - Chapter 9
    
    257
    
    Data Cache Load with a Data Dependency
    257
    
    Writeback Arbitration
    258
    
    Fastest External Load (Data Cache Miss)
    259
    
    Private Writeback Bus Load
    259
    
    A Full Completion Queue
    260
    
    Branch Instruction Handling
    260
    
    Branch Prediction
    261
    
    Instruction Timing List
    262
    
    Load/Store Instruction Timing
    263
    
    Accessing Off-Core Sprs
    264
    
    String Instruction Latency
    264
    
    Features
    270
  - Chapter 10
    
    271
    
    System Configuration and Protection
    271
    
    Multiplexing SIU Pins
    272
    
    Internal Memory Map Register (Immr)
    273
    
    Programming the SIU
    273
    
    SIU Module Configuration Register (SIUMCR)
    274
    
    System Protection Control Register (SYPCR)
    276
    
    Transfer Error Status Register (Tesr)
    277
    
    Register Lock Mechanism
    278
    
    Interrupt Structure
    279
    
    Priority of Interrupt Sources
    281
    
    Nonmaskable Interrupts—Irq0 and SWT
    282
    
    SIU Interrupt Processing
    282
    
    Programming the SIU Interrupt Controller
    283
    
    Siu Interrupt Pending Register (Sipend)
    283
    
    Siu Interrupt Mask Register (Simask)
    285
    
    Siu Interrupt Edge/Level Register (Siel)
    286
    
    Siu Interrupt Vector Register (Sivec)
    287
    
    The Bus Monitor
    288
    
    The Software Watchdog Timer
    289
    
    Software Service Register (Swsr)
    290
    
    The Powerpc Decrementer
    291
    
    Decrementer Register (Dec)
    292
    
    The Powerpc Timebase
    292
    
    Timebase Register (TBU and TBL)
    293
    
    Timebase Reference Registers (TBREFA and TBREFB)
    294
    
    Timebase Status and Control Register (Tbscr)
    294
    
    The Real-Time Clock
    295
    
    Real-Time Clock Status and Control Register (RTCSC)
    296
    
    Real-Time Clock Alarm Register (RTCAL)
    297
    
    Real-Time Clock Register (Rtc)
    297
    
    Real-Time Clock Alarm Seconds Register (RTSEC)
    298
    
    The Periodic Interrupt Timer (PIT)
    299
    
    Periodic Interrupt Status and Control Register (PISCR)
    300
    
    PIT Count Register (PITC)
    301
    
    PIT Register (PITR)
    301
    
    Freeze Operation
    302
    
    General SIU Timers Operation
    302
    
    Low-Power Stop Operation
    302
    
    Types of Reset
    303
  - Chapter 11
    
    304
    
    External Hard Reset
    304
    
    Internal Hard Reset
    304
    
    Power-On Reset
    304
    
    Checkstop Reset
    305
    
    Debug Port Hard or Soft Reset
    305
    
    JTAG Reset
    305
    
    PLL Loss of Lock
    305
    
    Software Watchdog Reset
    305
    
    External Soft Reset
    306
    
    Internal Soft Reset
    306
    
    Power-On and Hard Reset Sequence
    306
    
    Reset Status Register (RSR)
    307
    
    Soft Reset Sequence
    307
    
    Hard Reset
    309
    
    Hard Reset Configuration Word
    311
    
    Soft Reset
    313
    
    TRST and Power Mode Considerations
    313
  - Chapter 12
    
    325
    
    System Bus Signals
    325
    
    Active Pull-Up Buffers
    338
    
    Internal Pull-Up and Pull-Down Resistors
    339
    
    Bus Control Signals and Interrupts
    340
    
    Recommended Basic Pin Connections
    340
    
    JTAG and Debug Ports
    341
    
    Signal States During Hardware Reset
    341
    
    Unused Inputs
    341
    
    Unused Outputs
    341
  - Chapter 13
    
    343
    
    Bus Transfer Overview
    343
    
    Features
    343
    
    Bus Interface Signal Descriptions
    344
    
    Basic Transfer Protocol
    348
    
    Bus Operations
    348
    
    Single-Beat Transfer
    348
    
    Single-Beat Read Flow
    349
    
    Single-Beat Write Flow
    352
    
    Burst Transfers
    355
    
    Burst Operations
    356
    
    Alignment and Data Packing on Transfers
    365
    
    Arbitration Phase
    368
    
    Bus Grant (BG)
    369
    
    Bus Request (BR)
    369
    
    Bus Busy (BB)
    370
    
    Address Transfer Phase-Related Signals
    372
    
    External Bus Parking
    372
    
    Transfer Start (TS)
    372
    
    Address Bus
    373
    
    Address Types (AT)
    373
    
    Burst Indicator (BURST)
    373
    
    Read/Write (RD/WR)
    373
    
    Transfer Attributes
    373
    
    Transfer Size (TSIZ)
    373
    
    Burst Data in Progress (BDIP)
    376
    
    Burst Inhibit (BI)
    376
    
    Termination Signals
    376
    
    Termination Signals Protocol
    376
    
    Transfer Acknowledge (TA)
    376
    
    Transfer Error Acknowledge (TEA)
    376
    
    Memory Reservation
    377
    
    Kill Reservation (KR)
    378
    
    Bus Exception Control Cycles
    379
    
    Retry
    380
    
    Features
    385
    
    The Clock Module
    386
    
    External Reference Clocks
    387
  - Chapter 14
    
    388
    
    Crystal Oscillator Support (EXTAL and XTAL)
    388
    
    Off-Chip Oscillator Input (EXTCLK)
    388
    
    System PLL
    389
    
    SPLL Output Characteristics and Stability
    391
    
    The System Phase-Locked Loop Pins (VDDSYN, VSSSYN VSSSYN1, XFC)
    391
    
    Clock Signals
    392
    
    Disabling the SPLL
    392
    
    Clocks Derived from the SPLL Output
    393
    
    The Internal General System Clocks (GCLK1C, GCLK2C GCLK1, GCLK2)
    394
    
    Memory Controller and External Bus Clocks (GCLK1_50 GCLK2_50, CLKOUT)
    395
    
    CLKOUT Special Considerations: 1:2:1 Mode
    398
    
    The Baud Rate Generator Clock (BRGCLK)
    398
    
    The Synchronization Clock (SYNCCLK, SYNCCLKS)
    398
    
    The PIT and RTC Clock (PITRTCLK)
    399
    
    Power Distribution
    400
    
    The Time Base and Decrementer Clock (TMBCLK)
    400
    
    I/O Buffer Power (VDDH)
    401
    
    Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1)
    402
    
    Internal Logic Power (VDDL)
    402
    
    Keep-Alive Power (KAPWR)
    402
    
    Power Control (Low-Power Modes)
    402
    
    Doze High Mode
    405
    
    Normal High Mode
    405
    
    Normal Low Mode
    405
    
    Doze Low Mode
    406
    
    Deep-Sleep Mode
    407
    
    Sleep Mode
    407
    
    Power-Down Mode
    408
    
    Software Initiation of Power-Down Mode, with Automatic Wake-Up
    408
    
    Maintaining the Real-Time Clock (RTC) During Shutdown or Power Failure
    410
    
    Register Lock Mechanism: Protecting SIU Registers in Power-Down Mode
    410
    
    Clock and Power Control Registers
    411
    
    System Clock and Reset Control Register (SCCR)
    411
    
    TMIST: Facilitating Nesting of SIU Timer Interrupts
    411
    
    PLL, Low-Power, and Reset Control Register (PLPRCR)
    413
    
    Features
    417
    
    Basic Architecture
    420
    
    System Configuration
    421
    
    Chip-Select Programming Common to the GPCM and UPM
    422
    
    Address Space Programming
    423
    
    Address Type Protection
    423
    
    Memory Bank Write Protection
    423
    
    Register Programming Order
    423
    
    Memory Bank Protection Status
    424
    
    Base Registers (Brx)
    425
    
    Register Descriptions
    425
    
    Option Registers (Orx)
    426
    
    Memory Status Register (MSTAT)
    429
    
    Machine a Mode Register/Machine B Mode Registers (Mxmr)
    430
    
    Memory Command Register (MCR)
    431
    
    Memory Data Register (MDR)
    432
    
    Memory Address Register (MAR)
    433
    
    General-Purpose Chip-Select Machine (GPCM)
    434
    
    Memory Periodic Timer Prescaler Register (MPTPR)
    434
    
    Chip-Select Assertion Timing
    436
    
    Chip-Select and Write Enable Deassertion Timing
    437
    
    Relaxed Timing
    439
    
    Extended Hold Time on Read Accesses
    442
    
    Output Enable (OE) Timing
    442
    
    Boot Chip-Select Operation
    444
    
    External Asynchronous Master Support
    445
    
    Special Case: Bursting with External Transfer Acknowledge:
    446
    
    User-Programmable Machines (Upms)
    447
    
    Internal/External Memory Access Requests
    448
    
    Requests
    448
    
    Exception Requests
    449
    
    UPM Periodic Timer Requests
    449
    
    Control Signal Generation Timing
    450
    
    Programming the UPM
    450
    
    RAM Words
    453
    
    The RAM Array
    453
    
    Chip-Select Signals (Cstx)
    457
    
    Byte-Select Signals (Bstx)
    458
    
    General-Purpose Signals (Gxtx, G0X)
    459
    
    Loop Control (LOOP)
    460
    
    Address Multiplexing (AMX)
    461
    
    Exception Pattern Entry (EXEN)
    461
    
    Transfer Acknowledge and Data Sample Control (UTA, DLT3)
    466
    
    Disable Timer Mechanism (TODT)
    467
    
    Internal and External Synchronous Masters
    467
    
    The Last Word (LAST)
    467
    
    The Wait Mechanism (WAEN)
    467
    
    External Asynchronous Masters
    468
    
    Handling Devices with Slow or Variable Access Times
    469
    
    External Master Support
    470
    
    Hierarchical Bus Interface Example
    470
    
    Slow Devices Example
    470
    
    Synchronous External Masters
    470
    
    Address Incrementing for External Synchronous Bursting Masters
    471
    
    Asynchronous External Masters
    471
    
    Special Case: Address Type Signals for External Masters
    471
    
    UPM Features Supporting External Masters
    471
    
    External Master Examples
    472
    
    External Masters and the GPCM
    472
    
    Handshake Mechanism for Asynchronous External Masters
    472
    
    Special Signal for External Address Multiplexer Control
    472
    
    External Masters and the UPM
    474
    
    Memory System Interface Examples
    479
    
    Page-Mode DRAM Interface Example
    479
    
    Page Mode Extended Data-Out Interface Example
    490
    
    PCMCIA Cycle Control Signals
    501
    
    PCMCIA Input Port Signals
    502
    
    Operation Description
    503
    
    Other PCMCIA Signals
    503
    
    PCMCIA Output Port Signals (OP[0–4])
    503
    
    I/O Cards
    504
    
    Interrupts
    504
    
    Memory-Only Cards
    504
    
    Power Control
    505
    
    Reset and Three-State Control
    505
    
    PCMCIA Interface Input Pins Register (PIPR)
    506
    
    Programming Model
    506
    
    PCMCIA Interface Status Changed Register (PSCR)
    507
    
    PCMCIA Interface Enable Register (PER)
    508
    
    PCMCIA Interface General Control Register B (PGCRB)
    509
    
    PCMCIA Base Registers 0–7 (PBR0–PBR7)
    510
    
    PCMCIA Option Register 0–7 (POR0–POR7)
    510
    
    PCMCIA Controller Timing Examples
    514
    
    Communications Processor Module
    525
    
    SCC Ethernet Mode
    526
    
    Features
    531
    
    Risc Timer Tables
    532
    
    CPM General-Purpose Timers
    534
    
    Features
    535
    
    CPM Timer Operation
    536
    
    Timer Capture
    536
    
    Timer Clock Source
    536
    
    Timer Reference Count
    536
    
    Cascaded Mode
    537
    
    Timer Gating (Timers 1 and 2 Only)
    537
    
    CPM Timer Register Set
    538
    
    Timer 1 and SPKROUT
    538
    
    Timer Global Configuration Register (TGCR)
    538
    
    Timer Mode Registers (TMR1–TMR4)
    539
    
    Timer Capture Registers (TCR1–TCR4)
    540
    
    Timer Reference Registers (TRR1–TRR4)
    540
    
    Timer Counter Registers (TCN1–TCN4)
    541
    
    Timer Event Registers (TER1–TER4)
    541
    
    Timer Initialization Examples
    542
    
    Features
    543
    
    Communicating with the Core
    544
    
    Communicating with the Peripherals
    544
    
    CP Microcode Revision Number
    545
    
    CP Register Set and CP Commands
    546
    
    RISC Controller Configuration Register (RCCR)
    546
    
    RISC Microcode Development Support Control Register (RMDS)
    547
    
    Cp Command Register (Cpcr)
    548
    
    CP Commands
    549
    
    CP Command Examples
    551
    
    CP Command Execution Latency
    551
    
    Dual-Port RAM
    551
    
    System RAM and Microcode Packages
    553
    
    Parameter RAM
    554
    
    The Buffer Descriptor (BD)
    554
    
    The RISC Timer Table
    555
    
    RISC Timer Table Parameter RAM and Timer Table Entries
    556
    
    RISC Timer Table Scan Algorithm
    556
    
    Risc Timer Command Register (Tm_Cmd)
    557
    
    PWM Mode
    558
    
    RISC Timer Event Register (Rter)/Mask Register (RTMR)
    558
    
    RISC Timer Table Entries
    558
    
    RISC Timer Initialization
    559
    
    RISC Timer Interrupt Handling
    560
    
    Using the RISC Timers to Track CP Loading
    560
    
    SDMA Channels
    563
  - Chapter 19
    
    564
    
    SDMA Transfers
    564
    
    U-Bus Arbitration and the SDMA Channels
    564
    
    SDMA Registers
    565
    
    SDMA Configuration Register (SDCR)
    566
    
    Sdma Status Register (Sdsr)
    566
    
    IDMA Emulation
    567
    
    SDMA Address Register (SDAR)
    567
    
    SDMA Mask Register (SDMR)
    567
    
    IDMA Features
    568
    
    IDMA Parameter RAM
    568
    
    DMA Channel Mode Registers (DCMR)
    569
    
    IDMA Registers
    569
    
    IDMA Status Registers (IDSR1 and IDSR2)
    570
    
    IDMA Buffer Descriptors (BD)
    571
    
    IDMA Mask Registers (IDMR1 and IDMR2)
    571
    
    Function Code Registers—Sfcr and DFCR
    573
    
    Auto-Buffering and Buffer-Chaining
    574
    
    IDMA CP Commands
    574
    
    Activating an IDMA Channel
    575
    
    IDMA Channel Operation
    575
    
    IDMA Interface Signals—Dreq and SDACK
    575
    
    Suspending an IDMA Channel
    575
    
    IDMA Requests for Memory/Memory Transfers
    576
    
    IDMA Requests for Peripheral/Memory Transfers
    576
    
    Level-Sensitive Requests
    576
    
    Dual-Address (Dual-Cycle) Transfer
    577
    
    Edge-Sensitive Requests
    577
    
    IDMA Transfers—Dual-Address and Single-Address
    577
    
    Single-Address (Single-Cycle) Transfer (Fly-By)
    578
    
    Peripheral Write, Internally-Generated Ta
    579
    
    Single-Buffer Mode on IDMA1—A Special Case
    580
    
    IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode)
    581
    
    Idma1 Status Register (Idsr1) (Single-Buffer Mode)
    581
    
    Burst Timing (Single-Buffer Mode)
    582
    
    IDMA1 Mask Register (IDMR1) (Single-Buffer Mode)
    582
    
    External Recognition of an IDMA Transfer
    583
    
    Interrupts During an IDMA Bus Transfer
    584
  - Chapter 20
    
    586
    
    SI Features
    586
    
    The Time-Slot Assigner (TSA)
    587
    
    Enabling Connections to the TSA
    591
    
    TSA Signals
    591
    
    Disabling and Reenabling the TSA
    592
    
    Si Ram
    592
    
    SI RAM Dynamic Changes
    592
    
    Tdma Channel with Static Frames
    592
    
    Tdma Channel with Dynamic Frames
    594
    
    Programming the si RAM
    595
    
    SI RAM Programming Example
    597
    
    Si Global Mode Register (Sigmr)
    598
    
    Si Mode Register (Simode)
    598
    
    The si Registers
    598
    
    Si Clock Route Register (Sicr)
    604
    
    Si Command Register (Sicmr)
    606
    
    Si Status Register (Sistr)
    606
    
    Si Ram Pointer Register (Sirp)
    607
    
    IDL Bus Implementation
    608
    
    ISDN Terminal Adaptor Application
    609
    
    Programming the IDL Interface
    611
    
    GCI Bus Implementation
    612
    
    GCI Activation/Deactivation
    614
    
    Normal Mode
    614
    
    Programming the GCI Interface
    614
    
    SCIT Mode
    614
    
    GCI Interface (SCIT Mode) Programming Example
    615
    
    Baud Rate Generators (Brgs)
    618
    
    Baud Rate Generator Configuration Registers (Brgcn)
    620
    
    Autobaud Operation on the SCC UART
    621
    
    UART Baud Rate Examples
    622
  - Chapter 28 SCC Transparent Mode
    
    625
    
    Features
    626
  - Chapter 21
    
    627
    
    General SCC Mode Register (GSMR)
    627
    
    SCC Registers
    627
    
    Data Synchronization Register (DSR)
    633
    
    Transmit-On-Demand Register (Todr)
    634
    
    Scc Buffer Descriptors (Bds)
    635
    
    SCC Parameter RAM
    637
    
    Function Code Registers (Rfcr and Tfcr)
    639
    
    Handling SCC Interrupts
    639
    
    SCC Initialization
    640
    
    Controlling SCC Timing with RTS, CTS, and CD
    641
    
    Synchronous Protocols
    641
    
    Asynchronous Protocols
    644
    
    Digital Phase-Locked Loop (DPLL) Operation
    645
    
    Encoding Data with a DPLL
    647
    
    Clock Glitch Detection
    648
    
    Reset Sequence for an SCC Receiver
    650
    
    Reset Sequence for an SCC Transmitter
    650
    
    Saving Power
    650
    
    Switching Protocols
    650
  - Chapter 22 Scc Uart Mode
    
    651
    
    Features
    652
    
    Normal Asynchronous Mode
    653
    
    SCC UART Parameter RAM
    654
    
    Data-Handling Methods: Character- or Message-Based
    655
    
    Error and Status Reporting
    656
    
    SCC UART Commands
    656
    
    Multidrop Systems and Address Recognition
    657
    
    Receiving Control Characters
    657
    
    Hunt Mode (Receiver)
    659
    
    Inserting Control Characters into the Transmit Data Stream
    659
    
    Fractional Stop Bits (Transmitter)
    660
    
    Sending a Break (Transmitter)
    660
    
    Sending a Preamble (Transmitter)
    660
    
    Handling Errors in the SCC UART Controller
    661
    
    UART Mode Register (PSMR)
    662
    
    SCC UART Receive Buffer Descriptor (Rxbd)
    664
    
    Scc Uart Transmit Buffer Descriptor (Txbd)
    667
    
    SCC UART Event Register (SCCE) and Mask Register (SCCM)
    668
    
    SCC UART Status Register (SCCS)
    670
    
    SCC UART Programming Example
    671
    
    S-Records Loader Application
    672
  - Chapter 23
    
    676
    
    SCC HDLC Channel Frame Transmission
    676
    
    SCC HDLC Features
    676
    
    SCC HDLC Channel Frame Reception
    677
    
    SCC HDLC Parameter RAM
    677
    
    Programming the SCC HDLC Controller
    679
    
    SCC HDLC Commands
    679
    
    Handling Errors in the SCC HDLC Controller
    680
    
    Hdlc Mode Register (Psmr)
    681
    
    SCC HDLC Receive Buffer Descriptor (Rxbd)
    682
    
    Scc Hdlc Transmit Buffer Descriptor (Txbd)
    685
    
    HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
    686
    
    Hdlc Event Register (Scce)/Hdlc Mask Register (Sccm)
    687
    
    SCC HDLC Programming Example #1
    688
    
    SCC HDLC Programming Examples
    688
    
    SCC HDLC Status Register (SCCS)
    688
    
    HDLC Bus Mode with Collision Detection
    690
    
    SCC HDLC Programming Example #2
    690
    
    Accessing the HDLC Bus
    693
    
    HDLC Bus Features
    693
    
    Delayed RTS Mode
    694
    
    Increasing Performance
    694
    
    HDLC Bus Protocol Programming
    696
    
    Programming GSMR and PSMR for the HDLC Bus Protocol
    696
    
    Using the Time-Slot Assigner (TSA)
    696
    
    HDLC Bus Controller Programming Example
    697
  - Chapter 24
    
    699
    
    Operating the Localtalk Bus
    699
    
    Features
    700
    
    Connecting to Appletalk
    701
    
    Programming the GSMR
    701
    
    Programming the SCC in Appletalk Mode
    701
    
    Programming the PSMR
    702
    
    Programming the TODR
    702
    
    SCC Appletalk Programming Example
    702
    
    Irda Mode—Scc2 Only
    703
  - Chapter 25
    
    703
    
    Asynchronous HDLC Features
    703
    
    Asynchronous HDLC Frame Reception Processing
    704
    
    Asynchronous HDLC Frame Transmission Processing
    704
    
    Receiver Transparency Decoding
    705
    
    Transmitter Transparency Encoding
    705
    
    Exceptions to RFC 1549
    706
    
    Asynchronous HDLC Channel Implementation
    707
    
    Asynchronous HDLC Mode Parameter RAM
    707
    
    Asynchronous HDLC Commands
    709
    
    Data Synchronization Register (DSR)
    709
    
    General SCC Mode Register (GSMR)
    709
    
    Programming the Asynchronous HDLC Controller
    709
    
    Handling Errors in the Asynchronous HDLC Controller
    710
    
    Asynchronous HDLC Event Register (Scce)/Asynchronous HDLC Mask Register (SCCM)
    711
    
    SCC Asynchronous HDLC Registers
    711
    
    SCC Asynchronous HDLC Status Register (SCCS)
    712
    
    Asynchronous HDLC Mode Register (PSMR)
    713
    
    SCC Asynchronous HDLC Rxbds
    713
    
    SCC Asynchronous HDLC Txbds
    715
    
    Differences between HDLC and Asynchronous HDLC
    716
    
    SCC Asynchronous HDLC Programming Example
    717
  - Chapter 26
    
    720
    
    Features
    720
    
    SCC BISYNC Channel Frame Transmission
    720
    
    SCC BISYNC Channel Frame Reception
    721
    
    SCC BISYNC Parameter RAM
    722
    
    SCC BISYNC Commands
    723
    
    SCC BISYNC Control Character Recognition
    724
    
    BISYNC SYNC Register (BSYNC)
    725
    
    SCC BISYNC DLE Register (BDLE)
    726
    
    Handling Errors in the SCC BISYNC
    727
    
    Sending and Receiving the Synchronization Sequence
    727
    
    BISYNC Mode Register (PSMR)
    728
    
    SCC BISYNC Receive BD (Rxbd)
    730
    
    SCC BISYNC Transmit BD (Txbd)
    731
    
    BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
    733
    
    Programming the SCC BISYNC Controller
    734
    
    SCC Status Registers (SCCS)
    734
    
    SCC BISYNC Programming Example
    735
  - Chapter 27 Scc Ethernet Mode
    
    737
    
    Ethernet on the MPC850
    738
  - Chapter 35
    
    739
    
    Features
    739
  - Chapter 34 Parallel I/O Ports
    
    740
    
    Connecting the MPC850 to Ethernet
    740
    
    Learning Ethernet on the MPC850
    740
    
    SCC Ethernet Channel Frame Reception
    742
    
    SCC Ethernet Channel Frame Transmission
    742
    
    SCC Ethernet Parameter RAM
    743
    
    Programming the Ethernet Controller
    746
    
    SCC Ethernet Commands
    746
    
    SCC Ethernet Address Recognition
    747
    
    Hash Table Algorithm
    748
    
    Handling Collisions
    749
    
    Internal and External Loopback
    749
    
    Interpacket Gap Time
    749
    
    Full-Duplex Ethernet Support
    750
    
    Handling Errors in the Ethernet Controller
    750
    
    Ethernet Mode Register (PSMR)
    751
    
    SCC Ethernet Receive Buffer Descriptor
    752
    
    SCC Ethernet Transmit Buffer Descriptor
    754
    
    SCC Ethernet Event Register (Scce)/Mask Register (SCCM)
    756
    
    SCC Ethernet Programming Example
    757
    
    Features
    761
    
    SCC Transparent Channel Frame Reception Process
    762
    
    SCC Transparent Channel Frame Transmission Process
    762
    
    Achieving Synchronization in Transparent Mode
    763
    
    In-Line Synchronization Pattern
    763
    
    Synchronization in NMSI Mode
    763
    
    External Synchronization Example
    764
    
    External Synchronization Signals
    764
    
    End of Frame Detection
    765
    
    In-Line Synchronization Pattern
    765
    
    Synchronization and the TSA
    765
    
    Transparent Mode Without Explicit Synchronization
    765
    
    CRC Calculation in Transparent Mode
    766
    
    Inherent Synchronization
    766
    
    SCC Transparent Commands
    766
    
    SCC Transparent Parameter RAM
    766
    
    Handling Errors in the Transparent Controller
    767
    
    SCC Transparent Receive Buffer Descriptor (Rxbd)
    768
    
    Transparent Mode and the PSMR
    768
    
    SCC Transparent Transmit Buffer Descriptor (Txbd)
    770
    
    SCC Transparent Event Register (Scce)/Mask Register (SCCM)
    771
    
    SCC Status Register in Transparent Mode (SCCS)
    772
    
    SCC2 Transparent Programming Example
    773
  - Chapter 29
    
    776
    
    Low-Speed Irda Protocol
    776
    
    Middle-Speed Irda Protocol
    776
    
    High-Speed Irda Protocol
    777
    
    Data Link Layer
    778
    
    Serial Infrared Interaction Pulses
    779
    
    Infrared Mode Register (Irmode)
    780
    
    Irda Registers
    780
    
    Infrared Serial Interaction Control Register (Irsip)
    781
    
    Low-Speed Irda Programming
    782
    
    Middle-Speed Irda Programming
    783
    
    High-Speed Irda Programming Example
    784
  - Chapter 30 SMC Features
    
    788
    
    Smc Mode Registers (Smcmrn)
    789
    
    SMC Buffer Descriptors (Bds)
    791
    
    SMC Parameter RAM
    792
    
    Smc Function Code Registers (Rfcr/Tfcr)
    793
    
    Disabling Smcs On-The-Fly
    794
    
    SMC Transmitter Full Sequence
    794
    
    Changing SMC Protocols
    795
    
    Handling Interrupts in the SMC
    795
    
    Saving Power
    795
    
    SMC Receiver Full Sequence
    795
    
    SMC Receiver Shortcut Sequence
    795
    
    SMC Transmitter Shortcut Sequence
    795
    
    SMC in UART Mode
    796
    
    SMC UART Features
    796
    
    SMC UART Channel Transmission Process
    797
    
    SMC UART-Specific Parameter RAM
    797
    
    Data Handling Modes: Character- and Message-Oriented
    798
    
    SMC UART Channel Reception Process
    798
    
    Sending a Break
    799
    
    Sending a Preamble
    799
    
    SMC UART Commands
    799
    
    Handling Errors in the SMC UART Controller
    800
    
    Smc Uart Receive Bd (Rxbd)
    800
    
    Smc Uart Transmit Bd (Txbd)
    803
    
    SMC UART Event Register (Smce)/Mask Register (SMCM)
    804
    
    SMC UART Controller Programming Example
    805
    
    SMC in Transparent Mode
    806
    
    SMC Transparent Channel Transmission Process
    807
    
    SMC Transparent Mode Features
    807
    
    SMC Transparent Channel Reception Process
    808
    
    Using SMSYN for Synchronization
    808
    
    Using TSA for Synchronization
    809
    
    SMC Transparent Commands
    811
    
    Handling Errors in the SMC Transparent Controller
    812
    
    Smc Transparent Receive Bd (Rxbd)
    812
    
    Smc Transparent Transmit Bd (Txbd)
    813
    
    External Memory
    814
    
    SMC Transparent Event Register (Smce)/Mask Register (SMCM)
    815
    
    SMC Transparent NMSI Programming Example
    815
    
    SMC Transparent TSA Programming Example
    816
    
    SMC in GCI Mode
    817
    
    Handling the GCI Monitor Channel
    818
    
    SMC GCI Monitor Channel Reception Process
    818
    
    SMC GCI Monitor Channel Transmission Process
    818
    
    SMC GCI Parameter RAM
    818
    
    Handling the GCI C/I Channel
    819
    
    SMC GCI C/I Channel Reception Process
    819
    
    SMC GCI C/I Channel Transmission Process
    819
    
    SMC GCI Commands
    819
    
    SMC GCI Monitor Channel Rxbd
    819
    
    SMC GCI Monitor Channel Txbd
    820
    
    SMC GCI C/I Channel Rxbd
    821
    
    SMC GCI C/I Channel Txbd
    821
    
    SMC GCI Event Register (Smce)/Mask Register (SMCM)
    822
  - Chapter 18
    
    824
    
    Features
    824
    
    The SPI as a Master Device
    825
    
    The SPI as a Slave Device
    827
    
    The SPI in Multi-Master Operation
    827
    
    SPI Mode Register (SPMODE)
    829
    
    SPI Registers
    829
    
    SPI Transfers with Different Clocking Modes
    830
    
    SPI Examples with Different SPMODE[LEN] Values
    831
    
    Spi Command Register (Spcom)
    832
    
    Spi Event/Mask Registers (Spie/Spim)
    832
    
    SPI Parameter RAM
    833
    
    Receive/Transmit Function Code Registers (RFCR/TFCR)
    834
    
    SPI Buffer Descriptors (Bds)
    835
    
    SPI Commands
    835
    
    The SPI Buffer Descriptor (BD) Table
    835
    
    Spi Receive Bd (Rxbd)
    836
    
    Spi Transmit Bd (Txbd)
    837
    
    SPI Master Programming Example
    838
    
    SPI Slave Programming Example
    839
    
    Handling Interrupts in the SPI
    840
  - Chapter 31 SPI Clocking and Signal Functions
    
    824
  - Chapter 45
    
    841
    
    Overview
    841
    
    Features
    842
  - Chapter 32
    
    843
    
    Host Controller Limitations
    843
    
    USB Controller Signal Functions and Clocking
    843
    
    Sending and Receiving
    845
    
    USB Parameter RAM
    847
    
    Usb Mode Register (Usmod)
    850
    
    USB Registers
    850
    
    Usb Slave Address Register (Usadr)
    851
    
    USB Command Register (USCOM)
    852
    
    USB Event Register (Usber)/Mask Register (USBMR)
    853
    
    Usb Status Register (Usbs)
    854
    
    USB Buffer Descriptor Tables
    855
    
    Usb Receive Buffer Descriptor (Rxbd)
    857
    
    Usb Transmit Buffer Descriptor (Txbd)
    858
    
    USB CP Commands
    860
    
    USB Controller Errors
    861
    
    Programming the USB Host Controller
    862
    
    USB Host Controller Initialization Example
    863
    
    USB Function Controller Initialization Example
    864
  - Chapter 33
    
    868
    
    I2C Features
    868
    
    I2C Controller Transfers
    869
    
    I2C Registers
    872
    
    I2C Parameter RAM
    875
    
    I2C Commands
    877
    
    I2C Buffer Descriptor (BD) Tables
    878
    
    I 2 C Buffer Descriptors (Bds)
    879
    
    Features
    881
    
    Port a Data Register (Padat)
    883
    
    Port a Open-Drain Register (Paodr)
    883
    
    Port a Registers
    883
    
    Port a Data Direction Register (Padir)
    884
    
    Port a Pin Assignment Register (Papar)
    884
    
    Port a Functional Block Diagrams
    885
    
    Port B Open-Drain Register (Pbodr)
    888
    
    The Port B Registers
    888
    
    Port B Data Direction Register (Pbdir)
    889
    
    Port B Data Register (Pbdat)
    889
    
    Port B Pin Assignment Register (Pbpar)
    890
    
    Port C Data Register (Pcdat)
    893
    
    Port C Registers
    893
    
    Port C Data Direction Register (Pcdir)
    894
    
    Port C Pin Assignment Register (Pcpar)
    894
    
    Port C Special Options Register (PCSO)
    895
    
    Port C Interrupt Control Register (Pcint)
    896
    
    Port D Data Register
    897
    
    Port D Registers
    897
    
    Port D Data Direction Register (Pddir)
    898
    
    Port D Pin Assignment Register (PDPAR)
    898
    
    Features
    901
    
    CPM Interrupt Source Priorities
    903
    
    Programming Relative Priority (Grouping and Spreading)
    903
    
    Highest Priority Interrupt
    904
    
    Masking Interrupt Sources in the CPM
    904
    
    Nested Interrupts
    904
    
    Generating and Calculating Interrupt Vectors
    905
    
    CPIC Registers
    906
    
    CPM Interrupt Configuration Register (CICR)
    907
    
    CPM Interrupt Pending Register (CIPR)
    908
    
    CPM Interrupt In-Service Register (CISR)
    909
    
    CPM Interrupt Mask Register
    909
    
    Cpm Interrupt Vector Register (Civr)
    910
    
    Interrupt Handler Example—Single-Event Interrupt Source
    910
    
    Interrupt Handler Example—Multiple-Event Interrupt Source
    911
  - Chapter 38 ATM Parameter RAM
    
    913
    
    ATM Capabilities
    919
  - Chapter 36
    
    919
  - Chapter 39 ATM Controller
    
    919
    
    MPC850SR and MPC850 Differences
    919
    
    ATM Features
    920
    
    IDMA2 Restriction
    920
    
    The ATM Pace Controller (APC) and APC Timer
    920
  - Chapter 40 ATM Pace Control
    
    922
    
    MPC850SR Application Example
    922
    
    Overview of ATM Operation
    922
    
    UTOPIA Operation
    923
    
    UTOPIA Transmit Overview
    923
    
    UTOPIA Receive Overview
    924
    
    Expanded Cells
    925
    
    Serial ATM Operation
    925
    
    Serial ATM Receive Overview
    926
    
    Serial ATM Transmit Overview
    926
    
    Cell Delineation
    927
    
    Cell Payload Scrambling/Descrambling
    927
    
    ATM Pace Control (APC)
    928
    
    Internal and External Channels (Extended Channel Mode)
    928
    
    ATM Buffer Descriptors (Bds)
    929
  - Chapter 37
    
    930
    
    AAL5 Buffers
    930
    
    AAL0 Buffers
    931
    
    ATM Receive Buffer Descriptors (Rxbds)
    931
    
    ATM Transmit Buffer Descriptors (Txbds)
    935
    
    Receive and Transmit Connection Tables(Rcts and Tcts)
    937
    
    Receive Connection Table (Rct)
    938
  - Chapter 41 ATM Exceptions
    
    939
    
    Transmit Connection Table (Tct)
    940
    
    Atm Parameter Ram
    945
    
    Sar Receive Function Code Register (Srfcr)
    949
    
    Sar Receive State Register (Srstate)
    950
    
    Sar Transmit Function Code Register (Stfcr)
    951
    
    Sar Transmit State Register (Ststate)
    951
    
    Address Match Parameters (AM1–AM5)
    952
    
    Apc State Register (Apcst)
    955
    
    Serial Cell Synchronization Status Register (ASTATUS)
    956
    
    Serial Cell Synchronization Status Register (Astatus)
    957
    
    Address Mapping
    959
    
    Internal Look-Up Mechanism (SRSTATE[EXT] = 0)
    959
    
    Adding a New Internal Channel
    960
    
    Address Compression (SRSTATE[EXT,ACP] = 11)
    960
    
    Removing an Internal Channel
    960
    
    First-Level Addressing Table (FLT)
    961
    
    Second-Level Addressing Tables (Slts)
    961
    
    Address Compression Example
    962
    
    Preventing Channel Aliasing
    962
    
    CAM Address Mapping (SRSTATE[EXT,ACP] = 10)
    963
    
    OAM Screening
    963
    
    Setting Multi-PHY Mode
    963
    
    Look-Up Table MPHY Support
    964
    
    Receive Multi-PHY Operation
    964
    
    Address Compression Multi-PHY Support
    965
    
    APC Multi-PHY Parameters
    965
    
    ATM Commands
    965
    
    CAM Multi-PHY Support
    965
    
    Transmit Multi-PHY Operation
    965
    
    APC Algorithm
    969
    
    APC Implementation
    970
    
    APC Parameters
    971
    
    Programming APC Scheduling Table Size and NCITS
    972
    
    Programming Rates for Channels
    973
    
    APC Initialization and Operating Considerations
    974
    
    Minimizing Cell Delay Variation
    974
    
    Modifying Channel Transmit Pace
    974
    
    Direct Scheduling of Cells
    975
    
    Using the APC with Multiple ATM Ports
    975
    
    Using the APC Without Using UTOPIA
    976
    
    APC Scheduling Tables
    977
    
    APC Priority Levels
    978
    
    PHY Transmit Queues
    978
    
    ATM Event Registers
    982
    
    UTOPIA Event Register (IDSR1)
    982
    
    Serial ATM Event Register (SCCE)
    983
    
    Interrupt Queue Entry
    984
    
    Interrupt Queue Mask (IMASK)
    986
    
    Interface Conﬁguration
    987
  - Chapter 42 General ATM Registers
    
    987
    
    Port D Pin Assignment Register (PDPAR)
    987
    
    APC Timer (CPM Timer 4)
    988
    
    RISC Timer
    988
    
    System Clock Control Register (SCCR)
    988
    
    UTOPIA Interface
    988
    
    UTOPIA Mode Registers
    988
    
    Port B Multiplexing
    990
    
    Port C- Txclav and Rxclav Signals
    990
    
    Port D—UTOPIA Data and Control Signals
    990
    
    UTOPIA Mode Initialization
    991
    
    General SCC Mode Register (GSMR)
    992
    
    Serial ATM Mode Register (PSMR)
    992
  - Chapter 43
    
    995
    
    MPC850SR UTOPIA Interface Signals
    995
    
    UTOPIA Single-PHY
    997
    
    Receive Cell Transfer Operation
    998
    
    Transmit Cell Transfer Operation
    999
    
    UTOPIA Bus and SOC Drive
    999
    
    UTOPIA Multi-PHY Operations
    1000
    
    Receive Cell Transfer Operation
    1001
    
    Setting up PHSEL and PHREQ Pins
    1001
    
    Example MPHY Implementation
    1002
    
    Transmit Cell Transfer Operation
    1002
    
    UTOPIA Interface Transfer Timing
    1004
    
    Tracking Program Flow
    1009
  - Chapter 44
    
    1010
    
    Program Trace Functional Description
    1010
    
    Instruction Fetch Show Cycle Control
    1011
    
    Program Trace Signals
    1011
    
    Program Trace Special Cases
    1012
    
    Queue Flush Information Special Case
    1012
    
    Back Trace
    1013
    
    Program Trace When in Debug Mode
    1013
    
    Reconstructing Program Trace
    1013
    
    Sequential Instructions Marked as Indirect Branch
    1013
    
    Detecting the Trace Window Start Address
    1014
    
    Synchronizing the Trace Window to Internal Core Events
    1014
    
    Window Trace
    1014
    
    Detecting the Assertion/Negation of VSYNC
    1015
    
    Detecting the Trace Window End Address
    1015
    
    Watchpoints and Breakpoints Support
    1016
    
    Key Features
    1017
    
    Internal Watchpoints and Breakpoints Logic
    1018
    
    Functional Description
    1019
    
    Instruction Support Detailed Description
    1019
    
    Load/Store Support Detailed Description
    1020
    
    The Counters
    1022
    
    Byte and Half Word Working Modes
    1023
    
    Operation Details
    1023
    
    Restrictions
    1023
    
    Trap Enable Programming
    1023
    
    Examples
    1024
    
    Context Dependent Filter
    1025
    
    Ignore First Match
    1025
    
    Generating Six Compare Types
    1026
    
    Load/Store Breakpoint Example
    1026
    
    Development System Interface
    1027
    
    Debug Mode Operation
    1029
    
    Debug Mode Enable Vs. Debug Mode Disable
    1030
    
    Entering Debug Mode
    1031
    
    Checkstop State and Debug Mode
    1032
    
    Debug Mode Indication
    1032
    
    Exiting Debug Mode
    1033
    
    Running in Debug Mode
    1033
    
    Saving Machine State When Entering Debug Mode
    1033
    
    Development Port Communication
    1034
    
    Development Port Pins
    1034
    
    Development Serial Clock (DSCK)
    1034
    
    Development Serial Data in (DSDI)
    1034
    
    Development Serial Data out (DSDO)
    1034
    
    Development Port Registers
    1035
    
    Development Port Shift Register
    1035
    
    Freeze
    1035
    
    Asynchronous Clocked Mode—Using DSCK
    1036
    
    Development Port Registers Decode
    1036
    
    Development Port Serial Communications–Clock Mode
    1036
    
    Trap Enable Control Register (TECR)
    1036
    
    Synchronous Self-Clocked Mode—Using CLKOUT
    1037
    
    Development Port Serial Communications–Trap Enable Mode
    1038
    
    Selection of Development Port Clock Mode
    1038
    
    Serial Data into Development Port
    1039
    
    Serial Data out of Development Port
    1039
    
    Development Port Serial Communications–Debug Mode
    1040
    
    Serial Data into Development Port
    1040
    
    Serial Data out of Development Port
    1041
    
    Fast Download Procedure
    1042
    
    Development Support Programming Model
    1043
    
    Freeze Indication
    1043
    
    Software Monitor Debugger Support
    1043
    
    Comparator A–H Value Registers (CMPA–CMPH)
    1045
    
    Development Support Registers
    1045
    
    Breakpoint Address Register (BAR)
    1046
    
    Instruction Support Control Register (ICTRL)
    1047
    
    Load/Store Support Comparators Control Register (LCTRL1)
    1048
    
    Load/Store Support AND-OR Control Register (LCTRL2)
    1049
    
    Debug Mode Registers
    1052
    
    Interrupt Cause Register (ICR)
    1052
    
    Debug Enable Register (DER)
    1053
    
    Development Port Data Register (DPDR)
    1055
    
    Overview
    1057
    
    TAP Controller
    1058
    
    Boundary Scan Register
    1059
    
    Extest
    1062
    
    Instruction Register
    1062
    
    Sample/Preload
    1062
    
    Bypass
    1063
    
    Clamp
    1063
    
    Hi–Z
    1063
    
    Motorola MPC850 BSDL Description
    1064
    
    TAP Usage Considerations
    1064
    
    A.1 Byte Ordering Overview
    1065
    
    A.2 MPC850 Byte-Ordering Mechanisms
    1065
    
    A.4 TLE Mode
    1066
    
    A.4.1 TLE Mode System Examples
    1068
    
    A.5 PPC-LE Mode
    1070
    
    A.5.1 I/O Addressing in PPC-LE Mode
    1072
    
    A.6 Setting the Endian Mode of Operation
    1072
    
    B.1 Serial Clocking (Peak Rate Limitation)
    1075
    
    B.2 Bus Utilization
    1076
    
    B.3 CPM Bandwidth (Average Rate Limitation)
    1076
    
    B.3.1 Performance of Serial Channels
    1077
    
    B.3.2 IDMA Considerations
    1078
    
    B.3.3 Performance Calculations
    1079
    
    C.1 Powerpc Registers—User Registers
    1081
    
    C.2 Powerpc Registers—Supervisor Registers
    1082
    
    D.1 Instructions Sorted by Mnemonic
    1087
    
    D.2 Instructions Sorted by Opcode
    1095
    
    D.3 Instructions Grouped by Functional Categories
    1103
    
    D.4 Instructions Sorted by Form
    1113
    
    D.5 Instruction Set Legend
    1127
    
    E.1 MPC850 Overview
    1135
    
    E.1.1 Unimplemented Signals
    1136
    
    E.1.2 Serial Interface
    1137
    
    E.1.3 SCC General Set-Up
    1137
    
    E.1.4 Atm
    1137
    
    F.1 MPC850DSL Overview
    1139
    
    Serial ATM Configuration
    1169
    
    Communications Processor Module and Timers
    1177
  - Chapter 17 Communications Processor
    
    1178

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Motherboard Computer Hardware Microcontrollers Control Unit Controller

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Freescale Semiconductor MPC850SR Manuals

Freescale Semiconductor MPC850SR User Manual (1178 pages)

Table of Contents

Overview

Section 2

Chapter 16 System Configuration

Section 3

Appendix C

Appendix D

Appendix E

Chapter 1 Powerpc Microprocessor Module

Chapter 15 Memory Controller

Chapter 2 Memory Map

Chapter 3

Chapter 4 Powerpc User-Level Register Bit Assignments

Chapter 5

Chapter 6 Exception Ordering

Chapter 7

Chapter 8

Chapter 9

Chapter 10

Chapter 11

Chapter 12

Chapter 13

Chapter 14

Chapter 19

Chapter 20

Chapter 28 SCC Transparent Mode

Chapter 21

Chapter 22 Scc Uart Mode

Chapter 23

Chapter 24

Chapter 25

Chapter 26

Chapter 27 Scc Ethernet Mode

Chapter 35

Chapter 34 Parallel I/O Ports

Chapter 29

Chapter 30 SMC Features

Chapter 18

Chapter 31 SPI Clocking and Signal Functions

Chapter 45

Chapter 32

Chapter 33

Chapter 38 ATM Parameter RAM

Chapter 36

Chapter 39 ATM Controller

Chapter 40 ATM Pace Control

Chapter 37

Chapter 41 ATM Exceptions

Chapter 42 General ATM Registers

Chapter 43

Chapter 44

Chapter 17 Communications Processor

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