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The Time-Slot Assigner (TSA)
that are enabled by the SI RAM. The transmitter sends only the bits that are enabled by the
SI RAM and does not drive L1TXDa otherwise. L1TXDa is an open-drain output and
should be pulled high externally.
The MPC850 supports contention detection on the D channel of the SCIT bus. When the
MPC850 has data to send on the D channel, it checks an SCIT bus bit that is marked with
a special route code (usually, bit 4 of C/I channel 2). The physical layer device monitors the
physical layer bus for activity on the D channel and indicates on this bit that the channel is
free. If a collision is detected on the D channel, the physical layer device drives bit 4 of C/I
channel 2 to logic high. The MPC850 then aborts its transmission and resends the frame
when this bit is driven to logic low again. This procedure is automatically handled for the
first two buffers of a frame.
20.2.6.1 GCI Activation/Deactivation
In the deactivated state, the clock pulse is disabled and the data line is at a logic one. The
layer-1 device activates the MPC850 by enabling the clock pulses and sending an indication
on the C/I channel 0. To report the arrival of a valid indication in the SMC's RxBD, the
CPM sends a maskable interrupt to the core.
When the core activates the line, the data output of L1TXDa should be programmed to zero
by setting SIMODE[STZa]. Code 0 (command timing TIM) is sent on C/I channel 0 to the
layer-1 device until STZa is cleared. The physical layer device resumes the clock pulses and
gives an indication on C/I channel 0. The core should then clear STZa to enable data output.
20.2.6.2 Programming the GCI Interface
The two GCI interface modes, normal and SCIT, are described in the following sections.
20.2.6.2.1 Normal Mode
For normal mode operation, first program the channels' SIMODE[DSCa, FEa, CEa,
RFSDa] for GCI/SCIT mode, defining the sync pulse to GCI sync for framing and the data
clock as one-half the input clock rate. Also, if the receive and transmit sections are used to
interface with the same GCI bus, set SIMODE[CRTa] to internally connect the Rx clock
and sync signals to the SI RAM transmit section. Then define the GCI frame routing and
strobe select using the SI RAM.
When the receive and transmit sections use the same clock and sync signals, the sections
should use the same configuration. Also, L1TXDa in the I/O register should be configured
as an open-drain output. To support the monitor and C/I channels in GCI, those channels
should be routed to an SMC. To support the D channel when there is no possibility of
collision, clear SICR[GRa] for the SCC that supports the D channel.
20.2.6.2.2 SCIT Mode
To interface with the GCI/SCIT bus, configure SIMODE for basic GCI/SCIT operation.
Then program the SI RAM to support a 96-bit frame length and the frame sync to be the
GCI sync pulse. Generally, the SCIT bus supports the D channel access collision
mechanism. For this purpose, set SIMODE[CRTa] so the receive and transmit sections use
the same clock and sync signals and program SICR[GRa] to transfer the D channel grant
MPC850 Family User's Manual
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