Serial Data Into Development Port; Serial Data Out Of Development Port - Freescale Semiconductor MPC850 User Manual

44.3.2.4.1 Serial Data Into Development Port

The development port shift register is 35 bits wide, but trap enable mode transmissions only
use 10 of the 35 bits as the following—the start/ready bit, a mode/status bit, a control/status
bit, and the 7 least-significant data bits.
Table 44-10 shows the encoding of trap data shifted into the (through DSDI).
Table 44-10. Trap Enable Data Shifted into Development Port Shift Register
Start Mode Control
1 1 0
Table 44-11 shows the encoding of debug port command data shifted into the development
port shift register.
Table 44-11. Debug Port Command Shifted Into Development Port Shift Register
Start Mode Control
1 1 1
The watchpoint trap enables and VSYNC functions are described in Section 44.2,
"Watchpoints and Breakpoints Support," and Section 44.1, "Tracking Program Flow." The
debug port command function allows the development tool to either assert or negate
breakpoint requests, reset the processor, activate or deactivate the fast download procedure.

44.3.2.4.2 Serial Data Out of Development Port

In trap enable mode there is no data from the core out of the development port. Data out of
the development port in the trap enable mode is shown in Table 44-12.
1st 2nd 3rd 4th
Instruction
Watchpoint Trap Enables
0 = Disabled
1 = Enabled
Extended Opcode
x x
0 x
1 0
1 1
x x
x 0
x 1
0 x
1 x
Chapter 44. System Development and Debugging
Development System Interface
1st 2nd
Data VSYNC
Major Opcode
00000 NOP
00001 HRESET request
00010 SRESET request
00011 Reserved
00011 End download procedure
00011 Start download procedure
00100–11110 Reserved
11111 Negate maskable breakpoint
11111 Assert maskable breakpoint
11111 Negate nonmaskable breakpoint
11111 Assert nonmaskable breakpoint
Function
Transfer data to trap enable
control register
Function