Scc Bisync Channel Frame Reception - Freescale Semiconductor MPC850 User Manual

SCC BISYNC Channel Frame Reception

interrupt is issued according to TxBD[I]. TxBD[I] controls whether interrupts are generated
after transmission of each buffer, a specific buffer, or each block. The controller then
proceeds to the next BD.
If no additional buffers have been sent to the controller for transmission, an in-frame
underrun is detected and the controller starts sending syncs or idles. If the controller is in
transparent mode, it sends DLE-sync pairs. Characters are included in the block check
sequence (BCS) calculation on a per-buffer basis. Each buffer can be programmed
independently to be included or excluded from the BCS calculation; thus, excluded
characters must reside in a separate buffer. The controller can reset the BCS generator
before sending a specific buffer. In transparent mode, the controller inserts a DLE before
sending a DLE character, so that only one DLE is used in the calculation.
26.3 SCC BISYNC Channel Frame Reception
Although the receiver is designed to work with almost no core intervention, the user can
intervene on a per-byte basis if necessary. The receiver performs CRC16, longitudinal
(LRC) or vertical redundancy (VRC) checking, sync stripping in normal mode, DLE-sync
stripping, stripping of the first DLE in DLE-DLE pairs in transparent mode, and control
character recognition. Control characters are discussed in Section 26.6, "SCC BISYNC
Control Character Recognition."
When enabled, the receiver enters hunt mode where the data is shifted into the receiver shift
register one bit at a time and the contents of the shift register are compared to the contents
of DSR[SYN1, SYN2]. If the two are unequal, the next bit is shifted in and the comparison
is repeated. When registers match, hunt mode is terminated and character assembly begins.
The controller is character-synchronized and performs SYNC stripping and message
reception. It reverts to hunt mode when it receives an command, an error
ENTER HUNT MODE
condition, or an appropriate control character.
When receiving data, the controller updates the BCS bit in the BD for each byte transferred.
When the buffer is full, the controller clears the E bit in the BD and generates an interrupt
if the I bit in the BD is set. If incoming data exceeds the buffer length, the controller fetches
the next BD; if E is zero, reception continues to its buffer.
When a BCS is received, it is checked and written to the buffer. The BISYNC controller
sets the last bit, writes the message status bits into the BD, clears the E bit, and then
generates a maskable interrupt, indicating that a block of data was received and is in
memory. The BCS calculations do not include SYNCs (in nontransparent mode) or
DLE-SYNC pairs (in transparent mode).
Note that GSMR_H[RFW] should be set for an 8-bit-wide receive FIFO for the BISYNC
receiver. See Section 21.2.1, "General SCC Mode Register (GSMR)."
Chapter 26. SCC BISYNC Mode