Memory Periodic Timer Prescaler Register (Mptpr); General-Purpose Chip-Select Machine (Gpcm) - Freescale Semiconductor MPC850 User Manual

General-Purpose Chip-Select Machine (GPCM)

Table 15-9 describes MAR fields.
Bits Name
0–31 MA Contains a 32-bit address to be output on the address bus if AMX = 0b11. See Section 15.6.4.1, "RAM
Words."

15.4.8 Memory Periodic Timer Prescaler Register (MPTPR)

The memory periodic timer prescaler register (MPTPR) defines the divisor of the external
bus clock used as the memory periodic timer input clock. See Section 14.3, "Clock
Signals."
Bit 0 1 2
Field
Reset
R/W
Addr
Figure 15-14. Memory Periodic Timer Prescaler Register (MPTPR)
Table 15-10 describes MPTPR fields.
Bits Name
0–7 PTP
8–15 —
15.5 General-Purpose Chip-Select Machine (GPCM)
The GPCM allows a glueless and flexible interface between the MPC850, SRAM, EPROM,
FEPROM, ROM devices, and external peripherals. The GPCM contains three basic
configuration register groups—BRx, ORx, and MSTAT.
The GPCM provides a CS signal for memory bank activation, WE signals for write cycles
for each byte written to memory, and OE signals for read cycles. Figure 15-15 shows a
simple connection between an SRAM device and the MPC850.
Table 15-9. MAR Field Description
3 4 5 6
PTP
0000_001x
(IMMR & FFFF0000) + 0x17A
Table 15-10. MPTPR Field Descriptions
Periodic timers prescaler. Contains the division factor defined below.
001x xxxx Divide by 2.
0001 xxxx Divide by 4.
0000 1xxx Divide by 8.
0000 01xx Divide by 16.
0000 001x Divide by 32.
0000 0001 Divide by 64.
All other values are reserved.
Reserved, should be cleared.
MPC850 Family User's Manual
Description
7 8 9 10
0000_0000
R/W
Description
11 12 13 14
—
15