Single-Address (Single-Cycle) Transfer (Fly-By) - Freescale Semiconductor MPC850 User Manual

IDMA Emulation
source starting address, or destination starting address, IDMA uses the most efficient
packing algorithm possible to perform the transfer in the least number of bus cycles.

19.3.8.2 Single-Address (Single-Cycle) Transfer (Fly-By)

Each IDMA channel can be independently programmed to provide single-address, or
fly-by, transfers. The IDMA channel bypasses or flies-by internal storage since the transfer
occurs directly between a device and memory. DCMR[S/D] controls the direction of the
transfer. If DCMR[S/D] = 0b01, the IDMA controller handshakes with the peripheral for
the source data and writes to the destination memory address provided. If DCMR[S/D] =
0b10, the IDMA controller handshakes with the destination peripheral and reads from the
source memory address provided. The single-address read and write cycles are described
below.
• Single-address memory-read/peripheral-write—The memory address in SAPR, the
address type in SFCR, and the size in DCMR provide the data and control signals to
the data bus. This bus cycle operates like a normal read bus cycle. The SAPR is
incremented by 1, 2, or 4, according to the programming of DCMR[SIZE]. The
destination device is controlled by the IDMA handshake signals DREQ and
SDACK. Asserting SDACK provides write control to the destination device.
Figure 19-10 and Figure 19-11 show the transaction timing diagrams for
asynchronous and synchronous single-address peripheral writes. See Section 19.3.7,
"IDMA Interface Signals—DREQ and SDACK," for more on IDMA handshake
signals.
T3
CLKOUT
Address
TS
R/W
Data
TA
SDACK
Figure 19-10. SDACK Timing Diagram: Single-Address
T1 T3 T1 T3
Peripheral Write, Externally-Generated TA
MPC850 Family User's Manual
T1 T3 T1
T
SETUP
T
DELAY
T3 T1 T3
T
HOLD
T
PHOLD