The Time Base And Decrementer Clock (Tmbclk); Power Distribution - Freescale Semiconductor MPC850 User Manual

Power Distribution

The MODCK[1-2] state at PORESET deassertion determines the input clock source and
prescaler value for PITRTCLK. These values can be changed after reset by manipulating
the associated bits in the SCCR.
Table 14-4. PITRTCLK Configuration at PORESET
MODCK [1:2]

14.3.3 The Time Base and Decrementer Clock (TMBCLK)

The time base and decrementer clock is generated either from the input frequency of the
SPLL (OSCCLK) or the general system clock GCLK2. The SCCR[TBS] bit is used to
select between these two sources.
The MODCK[1-2] state at PORESET deassertion, the SCCR[TBS], and the SPLL
multiplication factor determine the input clock source and prescaler value for TMBCLK.
SCCR[TBS]
1
0
0
0
14.4 Power Distribution
The various modules of the MPC850 are connected to four distinct power rails. These
power rails have different requirements, as explained in the following sections. The
organization of the power rails is shown in Figure 14-12.
PITRTCLK Prescaler
SCCR[RTDIV]
00 4
01 512
10 512
11 512
Table 14-5. TMBCLK Configuration
MODCK[1-2] at
PORESET
XX
0X
1X
1X
MPC850 Family User's Manual
PITRTCLK Input Source
SCCR[RTSEL]
OSCM (crystal oscillator)
OSCM (crystal oscillator)
EXTCLK
EXTCLK
MF + 1 Clock Source
X GCLK2
X OSCCLK
1, 2 OSCCLK
> 2 OSCCLK
TMBCLK Prescaler
16
4
16
4