Signal
PDPAR = 0
PD15
Port D15
PD14
Port D14
PD13
Port D13
PD12
Port D12
PD11
Port D11
PD10
Port D10
PD9
Port D9
PD8
Port D8
PD7
Port D7
PD6
Port D6
PD5
Port D5
PD4
Port D4
PD3
Port D3
42.2.5 RISC Controller Configuration Register (RCCR)
The RCCR[DR1M,DR0M] bits must be set (level-sensitive IDMA request signals) to
enable UTOPIA operation. Also, program RCCR[DRQP] to 0b01 to give SCC transfers
higher priority.
42.2.6 UTOPIA Mode Initialization
The following procedure is required for proper initialization of the UTOPIA interface:
1. Because the UTOPIA port activates immediately upon initialization, configure the
ATM parameters and data structures first.
2. Program PCPAR, PCDIR, and PCSO to enable TxClav and RxClav.
The ATM controller starts searching for SOC and sets SRSTATE[SNC] as soon as the first
SOC is found.
Table 42-3. Port D Pin Assignment
PDPAR=1
UT=0
PDDIR=0
PDDIR=1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Chapter 42. Interface Configuration
UTOPIA Mode Registers
Input to On-Chip
Peripherals
UT=1
UTPB[0]
—
UTPB[1]
—
UTPB[2]
—
UTPB[3]
—
RxEnb
—
TxEnb
—
UtpClk
—
—
—
UTPB[4]
—
UTPB[5]
—
UTPB[6]
—
UTPB[7]
—
SOC
—