Tdma Channel With Dynamic Frames - Freescale Semiconductor MPC850 User Manual

The Time-Slot Assigner (TSA)
1)
2)
3)
Figure 20-5. SI RAM Dynamic Changes with TDMa
The entire SI RAM is always readable, but only the shadow RAM is safe to write. The SI
status register (SISTR) can be read to determine which part of the RAM is the current-route
RAM. The SI RAM pointer (SIRP) register can be used to determine which SI RAM entry
is active. In addition, by externally connecting a strobe to an interrupt signal, an individual
SI RAM entry can generate an interrupt.

20.2.3.4 TDMa Channel with Dynamic Frames

In an SI configuration using the one TDM channel with dynamic frames, TDMa has 32
entries apiece for Tx and Rx data/strobe routing, as shown in Figure 20-6. One RAM
Initial State RAM address:
The TSA uses the first part of
the RAM, and the shadow is
the second part of the RAM.
CSRxa = 0
Framing Signals:
CSRRa=0 RAM Address:
CSRTa=0
Framing Signals:
RAM Address:
Programming
Program the shadow
RAM for the new
Rx and Tx route and set
CSRxa.
Framing Signals:
CSRRa=1 RAM Address:
CSRTa=1
Framing Signals:
Exchange RAM Address:
The SI exchanges between
the shadow and the
current-route RAMs
and resets CSRxa.
Framing Signals:
CSRRa=0 RAM Address:
CSRTa=0
Framing Signals:
MPC850 Family User's Manual
0 127 128
32 RXa 32 RXa
Route Shadow
L1RCLKa
L1RSYNCa
256 383 384
32 TXa 32 TXa
Route Shadow
L1TCLKa
L1TSYNCa
0 127 128
32 RXa 32 RXa
Route Shadow
L1RCLKa
L1RSYNCa
256 383 384
32 TXa 32 TXa
Route Shadow
L1TCLKa
L1TSYNCa
0 127 128
32 RXa 32 RXa
Shadow Route
L1RCLKa
L1RSYNCa
256 383 384
32 TXa
32 TXa
Shadow
Route
L1TCLKa
L1TSYNCa
255
511
255
511
255
511