Smc Parameter Ram - Freescale Semiconductor MPC850 User Manual

Common SMC Settings and Configurations
The BD table allows buffers to be defined for transmission and reception. Each table forms
a circular queue. The CP uses BDs to confirm reception and transmission so that the
processor knows buffers have been serviced. The data resides in external or internal buffers.
When SMCs are configured to operate in GCI mode, their memory structure is predefined
to be one half-word long for transmit and one half-word long for receive. For more
information on these half-word structures, see Section 30.5, "SMC in GCI Mode."

30.2.3 SMC Parameter RAM

Each SMC parameter RAM area begins at the same offset from each SMC base. The
protocol-specific portions of the SMC parameter RAM are discussed in the sections that
follow. The SMC parameter RAM shared by the UART and transparent protocols is shown
in Table 30-2. Parameter RAM for GCI protocol is described in Section 30.5.1, "SMC GCI
Parameter RAM."
Table 30-2. SMC UART and Transparent Parameter RAM Memory Map
1
Offset Name Width
RBASE
0x00 Hword RxBDs and TxBDs base address. (BD table pointer) Define starting points in the
TBASE
0x02 Hword
RFCR
0x04 Byte
TFCR
0x05 Byte
0x06 MRBLR Hword Maximum receive buffer length. The most bytes the MPC850 writes to a Rx buffer before
0x08 RSTATE Word
0x0C — Word
0x10 RBPTR Hword RxBD pointer. Points to the next BD for each SMC channel that the receiver transfers
0x12 — Hword Rx internal byte count.
dual-port RAM of the set of BDs for the SMC send and receive functions. They allow
flexible partitioning of the BDs. By selecting RBASE and TBASE entries for all SMCs
and by setting W in the last BD in each list, BDs are allocated for the send and receive
side of every SMC. Initialize these entries before enabling the corresponding channel.
Configuring BD tables of two enabled SMCs to overlap causes erratic operation.
RBASE and TBASE should be a multiple of eight.
Rx/Tx function code. See Section 30.2.3.1, "SMC Function Code Registers
(RFCR/TFCR)."
moving to the next buffer. It can write fewer bytes than MRBLR if a condition like an error
or end-of-frame occurs, but it cannot exceed MRBLR. Rx buffers should not be smaller
than MRBLR. SMC Tx buffers are unaffected by MRBLR.
Tx buffers can be individually given varying lengths through the data length field.
MRBLR can be changed while an SMC is operating only if it is done in a single bus cycle
with one 16-bit move (not two 8-bit bus cycles back-to-back). This occurs when the CP
shifts control to the next RxBD, so the change does not take effect immediately. To
guarantee the exact RxBD on which the change occurs, change MRBLR only while the
SMC receiver is disabled. MRBLR should be greater than zero and should be even if
character length exceeds 8 bits.
Rx internal state. Can be used only by the CP.
2
Rx internal data pointer. Updated by the SDMA channels to show the next address in
the buffer to be accessed.
data to when it is in idle state, or to the current BD during frame processing. After a reset
or when the end of the BD table is reached, the CP initializes RBPTR to the value in
RBASE. Most applications never need to write RBPTR, but it can be written when the
receiver is disabled or when no receive buffer is in use.
2
A down-count value initialized with the MRBLR value and
decremented with every byte the SDMA channels write.
MPC850 Family User's Manual
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