Pcmcia Input Port Signals - Freescale Semiconductor MPC850 User Manual

PCMCIA Module Signal Definitions
Table 16-1. PCMCIA Cycle Control Signals (Continued)
Signal
ALE_B Address latch enable. Output strobe that controls the external latches of the address and REG
signalsALE_B is asserted when socket B is accessed. Note that latches are used when power consumption
is an issue. They keep the PCMCIA signals from toggling unnecessarily when the PCMCIA cards are not
being accessed. If power consumption is not an issue, buffers can be used instead of ALE_x signals.
IOIS16_B I/O port is 16 bits. Input. Applies only when the card and its socket are programmed for I/O interface
operation. Must be asserted by the card when the address on the bus corresponds to an address on the PC
card and the I/O port being addressed supports 16-bit accesses. If the I/O region in which the address
resides is programmed as 8 bits wide, IOIS16_B is ignored.

16.2.2 PCMCIA Input Port Signals

The following signals are used by a PCMCIA slot to indicate card status. The MPC850
provides synchronization, transition detection, optional interrupt generation, and the means
for the software to read the signal state. This function is not necessarily specific to
PCMCIA; a system can use these signals as a general-purpose input port with edge
detection and interrupt capability. These signals appear on pins IP_B[0–7]. All these signals
are symmetrical except IP_B7, which has extended edge detection capability and IP_B2,
which serves as an IOIS16_B cycle-control signal for PCMCIA cycles.
Signal
VS1_B, Voltage sense. Input. Used as VS1 and VS2 and generated by PC cards. They notify the socket of the
VS2_B card V requirement. These signals are connected to IP_B[0–1].
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WP Write protect. Input. When the card and socket are programmed for memory interface operation, this
signal is used as WP. It reflects the state of the write-protect switch on the PC card. The PC card must
assert WP when the card switch is enabled. It must be negated when the switch is disabled. For a PC card
that is writable without a switch, WP must be connected to ground. If the PC card is permanently
write-protected, WP must be connected to V
CD1_B, Card detect. Input. Provide proper detection of card insertion. They must be connected to ground
CD2_B internally on the PC card, thus, these signals are forced low when a card is placed in the socket. These
signals must be pulled up to system V
powered down. These signals are connected IP_B4 and IP_B3, respectively.
BVD1_B, Battery voltage detect. Input. When the card and its socket are programmed for memory interface
BVD2_B operation, these signals are used as BVD1_B and BVD2_B and are generated by PC cards with on-board
batteries to report the battery condition. Both BVD1_B and BVD2_B must be held asserted when the
battery is in good condition. Negating BVD2_B while keeping BVD1_B asserted indicates the battery is in
a warning condition and should be replaced, although data integrity on the card is still assured. Negating
BVD1_B indicates that the battery is no longer serviceable and data is lost, regardless of the state of
BVD2_B. These signals are connected to IP_B6 and IP_B5, respectively.
STSCHG_B Status change. Input. When the card and its socket are programmed for I/O interface operation, BVD1_B
is used as STSCHG_B and is generated by I/O PC cards. STSCHG_B must be held negated when the
"signal on change" bit and "changed" bit in the card status register on the PC card are either or both zero.
STSCHG_B must be asserted when both bits = 1.
Table 16-2. PCMCIA Input Port Signals
to allow card detection to function while the card socket is
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MPC850 Family User's Manual
Description
Description
. These signals are connected to IP_B2 pins.
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