Serial Cell Synchronization Status Register (Astatus) - Freescale Semiconductor MPC850 User Manual

Serial Cell Synchronization Status Register (ASTATUS)

Table 38-12. APCST Field Descriptions (Continued)
Bit(s) Name
5–7 NMPHY Number of (multiple) PHYs. Valid only when in UTOPIA multi-PHY mode; in all other parameter
RAM pages (SCC2–3), this field should be cleared. NMPHY specifies the total number of PHY
devices connected to the UTOPIA port.
000 1 PHY
001 2 PHYs
010 3 PHYs
011 4 PHYs
1xx Reserved
8–10 CMPHY Current multi-PHY. Valid only when in UTOPIA multi-PHY mode. CMPHY is used only by the CP
and should be initialized with the same value programmed in NMPHY.
11 — Reserved
12 — Reserved
13 DIS APC disabled status flag. Valid for serial ATM only. Set by the transmitter when a global FIFO
underrun (GUN) exception occurs. Should be cleared during initialization.
14 PL2 Priority level 2—classic SAR only. Enables the second APC priority level.
0 Disable the second-level APC scheduling table.
1 Enable the second-level APC scheduling table.
15 MPY Enable multi-PHY mode Valid only for page 4 of the parameter RAM when in UTOPIA mode. For
additional information about the multi-PHY configuration, see Section 39.2.1, "Setting
Multi-PHY mode."
0 Single PHY mode
1 Multiple PHY mode
38.7 Serial Cell Synchronization Status Register
(ASTATUS)
The serial ATM cell synchronization status register (ASTATUS) provides status
information concerning FIFO errors and receiver synchronization status. The ASTATUS
register is shown in Figure 38-8.
0 1 2 3
— — — —
Figure 38-8. Serial Cell Synchronization Status Register (ASTATUS)
The ASTATUS fields are described inTable 38-13.
Table 38-13. ASTATUS Register Field Descriptions
Bits Name
0–5 — Reserved
6 ORUN Receiver FIFO overrun. The CP sets this flag to indicate a receiver overrun event has occurred.
The user can acknowledge the flag by clearing it.
0 No receiver FIFO overrun
1 Receiver FIFO overrun. Note that the SCCE[GOV] bit is also set.
4 5 6 7
— — ORUN URUN
MPC850 Family User's Manual
Description
8 9 10 11 12
— — — — —
Description
13 14 15
— — LOCK