The Si Registers; Si Global Mode Register (Sigmr); Si Mode Register (Simode) - Freescale Semiconductor MPC850 User Manual

The Time-Slot Assigner (TSA)

20.2.4 The SI Registers

The following sections describe the SI registers.

20.2.4.1 SI Global Mode Register (SIGMR)

The SI global mode register (SIGMR), shown in Figure 20-9, defines the SI RAM division
modes and enables the TDM channel.
Bit 0
Field
Reset
R/W
Addr
Table 20-4 describes the SIGMR fields.
Bits Name
0–4 — Reserved, should be cleared.
5 ENa Enable TDMa.
0 TDMa is disabled. SI RAM and TDM routing are in a state of reset; all other SI functions still operate.
1 TDMa is enabled.
6–7 RDM RAM division mode. Defines the SI RAM partitioning based on whether dynamic changes are needed.
00 Static TDMa with 64 entries apiece for Rx and Tx routing.
01 Dynamic TDMa with 32 entries apiece for current-route and shadow Rx routing and 32 apiece for
current-route and shadow Tx routing.
1x Reserved.
Note that after setting SIGMR[ENa], data from the transmit buffers does not immediately
appear at the TDM transmit pin with the first frame because the SCCs require start-up
clocking at initialization. Expect a number of bytes of idle (typically 10–15) depending on
the size of the frame and number of time slots routed to the particular SCC.

20.2.4.2 SI Mode Register (SIMODE)

The SI mode register (SIMODE), shown in Figure 20-10, defines the SI operation modes
for the TDM channel and SMCs.
1 2
—
Figure 20-9. SI Global Mode Register (SIGMR)
Table 20-4. SIGMR Field Descriptions
MPC850 Family User's Manual
3 4
— ENa
0
R/W
0xAE4
Description
5 6
RDM
7