Scc Hdlc Channel Frame Reception; Scc Hdlc Parameter Ram - Freescale Semiconductor MPC850 User Manual

SCC HDLC Channel Frame Reception

The command can be used to expedite critical data ahead of previously
STOP TRANSMIT
linked buffers or to support efficient error handling. When the SCC receives a
STOP
command, it sends idles or flags instead of the current frame until it receives a
TRANSMIT
command. The command can be used to
RESTART TRANSMIT GRACEFUL STOP TRANSMIT
insert a high-priority frame without aborting the current one—a graceful-stop-complete
event is generated in SCCE[GRA] when the current frame is finished. See Section 23.6,
"SCC HDLC Commands."
23.3 SCC HDLC Channel Frame Reception
The HDLC receiver is designed to work with little or no core intervention to perform
address recognition, CRC checking, and maximum frame length checking. Received
frames can be used to implement any HDLC-based protocol.
Once enabled by the core, the receiver waits for an opening flag character. When it detects
the first byte of the frame, the SCC compares the frame address with four
user-programmable, 16-bit address registers and an address mask. The SCC compares the
received address field with the user-defined values after masking with the address mask. To
detect broadcast (all ones) address frames, one address register must be written with all
ones.
If an address match is detected, the SCC fetches the next BD and SCC starts transferring
the incoming frame to the buffer if it is empty. When the buffer is full, the SCC clears
RxBD[E] and generates a maskable interrupt if RxBD[I] is set. If the incoming frame is
larger than the current buffer, the SCC continues receiving using the next BD in the table.
During reception, the SCC checks for frames that are too long (using MFLR). When the
frame ends, the CRC field is checked against the recalculated value and written to the
buffer. RxBD[Data Length] of the last BD in the HDLC frame contains the entire frame
length. This also enables software to identify the frames in which the maximum frame
length violations occur. The SCC sets RxBD[L] (last buffer in frame), writes the frame
status bits, and clears RxBD[E]. It then generates a maskable event (SCCE[RXF]) to
indicate a frame was received. The SCC then waits for a new frame. Back-to-back frames
can be received with only one shared flag between frames.
The received frames threshold parameter (RFTHR) can be used to postpone interrupts until
a specified number of frames is received. This function can be combined with a timer to
implement a timeout if fewer than the specified number of threshold frames is received.
Note that an SCC in HDLC mode, or any other synchronous mode, must receive a
minimum of eight clocks after the last bit arrives to account for Rx FIFO delay.

23.4 SCC HDLC Parameter RAM

For HDLC mode, the protocol-specific area of the SCC parameter RAM is mapped as in
Table 23-1.
Chapter 23. SCC HDLC Mode