Unsupported Registers; Powerpc Supervisor-Level Register Bit Assignments; Machine State Register (Msr) - Freescale Semiconductor MPC850 User Manual

MPC850 Register Implementation
a valid value only when a data breakpoint exception is taken. At any other time, its
value is boundedly undefined (this term is defined very specifically by the PowerPC
architecture and is discussed in the Programming Environments Manual).
The following situations cause the DAR, BAR, and DSISR registers to be updated.
Table 4-7. Value Summary of the DAR, BAR, and DSISR Registers
Exception Type
DSI
Alignment
Data breakpoint
Machine check
Software emulation exception
Floating-point unavailable
Program exception

4.1.2.2 Unsupported Registers

The MPC850 does not support the following OEA registers:
• DBATs and IBATs —The MPC850 does not support block address translation.
• EAR—The MPC850 does not support the optional external access facility.
• SDR1—The MPC850 does not support memory segments.
• Segment registers—The MPC850 does not support memory segments.

4.1.2.3 PowerPC Supervisor-Level Register Bit Assignments

This section describes bit assignments of supervisor-level PowerPC registers implemented
by the MPC850. For more details, see the Programming Environments Manual for 32-Bit
Processors.

4.1.2.3.1 Machine State Register (MSR)

The 32-bit machine state register (MSR) is used to configure such parameters as the
privilege level, whether translation is enabled, and the endian-mode. It can be read by the
mfmsr instruction and modified by the mtmsr, sc, and rfi instructions.
DAR Value
Cycle EA
Data EA
Does not change
Cycle EA
Does not change
Does not change
Does not change
MPC850 Family User's Manual
DSISR Value
Data MMU error status
Instruction information
Does not change
Instruction information
Does not change
Does not change
Does not change
BAR Value
Undefined
Undefined
Cycle EA
Undefined
Undefined
Undefined
Does not change