Tracking Program Flow - Freescale Semiconductor MPC850 User Manual

Chapter 44
System Development and Debugging
Emulators require a level of control and observation that is in sharp contrast to the trend of
modern microcomputers and microprocessors in which many bus cycles are directed to
internal resources and are not externally visible. The same is true for bus analyzers. To help
development tools support, some development support functions are implemented in the
silicon. Program flow tracking, internal watchpoint and breakpoint generation, and
emulation systems control over the activity of the core (debug mode) are some of the
features that allow the user to efficiently debug MPC850-based systems.

44.1 Tracking Program Flow

The MPC850 provides many options for tracking program flows that impact performance
in varying degrees.
• In one mode, signals provided for tracking code flow can be captured externally and
then parsed by a post-processing program. This mode is described more fully in
subsequent sections.
• In another, slower mode, instruction flow is visible on the external bus when the
MPC850 is programmed to operate in serialized mode with all fetch cycles shown
on the external bus. Although instruction flow tracking is simpler, performance is
much lower than in regular mode. Section 44.5.1.3, "Instruction Support Control
Register (ICTRL)," describes programming of the core to operate in this mode.
The MPC850 implements a prefetch queue combined with parallel, out-of-order, and
pipelined execution. These features, plus the fact that most fetch cycles are performed
internally (from the I-cache), increase performance but make it very difficult to provide the
user with the real program trace. Instructions progress inside the core from fetch to
retirement. An instruction retires from the machine only after it and all preceding
instructions finish execution with no exception. Therefore, only retired instructions can be
considered architecturally executed.
To reconstruct program trace, the program code, combined with additional MPC850
information, is required. Reporting program trace during retirement significantly
complicates the implementation in two ways: more than one instruction can retire in a clock
cycle; and, it is harder to report on indirect branches during retirement. Because of this,
program trace is deciphered by monitoring fetched code and instruction queue flushes, and
Chapter 44. System Development and Debugging