Debug Enable Register (Der) - Freescale Semiconductor MPC850 User Manual

Table 44-24. ICR Field Descriptions (Continued)
Bits Name
7 ALI Alignment interrupt bit. Set when the alignment interrupt is asserted. Causes debug mode entry
if debug mode is enabled and the corresponding enable bit is set.
8 PRI Program interrupt bit. Set when the program interrupt is asserted. Causes debug mode entry if
debug mode is enabled and the corresponding enable bit is set.
9 FPUVI Floating-point unavailable interrupt bit. Set when the floating-point unavailable interrupt is
asserted. Causes debug mode entry if debug mode is enabled and the corresponding enable bit
is set.
10 DECI Decrementer interrupt bit. Set when the decrementer interrupt is asserted. Causes debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
11–12 — Reserved
13 SYSI System call interrupt bit. Set when the system call interrupt is asserted. Causes debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
14 TR Trace interrupt bit. Set when in single-step mode or when in branch trace mode. Causes debug
mode entry if debug mode is enabled and the corresponding enable bit is set.
15–16 — Reserved
17 SEI Implementation-dependent software emulation interrupt. Set when the floating-point assist
interrupt is asserted. Causes debug mode entry if debug mode is enabled and the corresponding
enable bit is set.
18 ITLBMS Implementation-specific ITLB miss. Set as a result of an ITLB miss. Causes debug mode entry if
debug mode is enabled and the corresponding enable bit is set.
19 DTLBMS Implementation-specific DTLB miss. Set as a result of an DTLB miss. Causes debug mode entry
if debug mode is enabled and the corresponding enable bit is set.
20 ITLBER Implementation-specific ITLB error. Set as a result of an ITLB error. Causes debug mode entry if
debug mode is enabled and the corresponding enable bit is set.
21 DTLBER Implementation-specific DTLB error. Set as a result of an DTLB error. results in debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
22–27 — Reserved
28 LBRK Load/store breakpoint interrupt bit. Set as a result of the assertion of an load/store breakpoint.
Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set.
29 IBRK Instruction breakpoint interrupt bit. Set as a result of the assertion of an instruction breakpoint.
Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set.
30 EBRK External breakpoint interrupt bit (development port, internal or external modules). Set as a result
of the assertion of an external breakpoint. Causes debug mode entry if debug mode is enabled
and the corresponding enable bit is set.
31 DPI Development port interrupt bit. Set by the development port as a result of a debug station
nonmaskable request or when entering debug mode immediately out of reset. Causes debug
mode entry if debug mode is enabled and the corresponding enable bit is set.

44.5.2.2 Debug Enable Register (DER)

The DER, shown in Figure 44-23, lets the user selectively enable events that can cause the
processor to enter debug mode. Its reset value is 0x0200_2000.
Chapter 44. System Development and Debugging
Development Support Programming Model
Description