Idma Status Registers (Idsr1 And Idsr2) - Freescale Semiconductor MPC850 User Manual

IDMA Emulation
Table 19-5 describes DCMR fields.
Bits Name
0–10 — Reserved. Should be cleared.
SIZE
11–12 Peripheral port size. Determines the operand transfer size per DREQx assertion for
peripheral/memory transfers, but not for memory/memory transfers. (For memory/memory
transfers the size is determined only by address alignment and the amount of data remaining to be
transferred.)
00 Word length.
01 Half-word length.
10 Byte length.
11 Reserved.
Note that the memory port size is transparent to the IDMA. The SIU emulates a 32-bit port size
regardless of the actual memory port size.
S/D
13–14 Source/destination. Defines the source and destination—memory or peripheral.
00 Read from memory; write to memory.
01 Read from peripheral; write to memory.
10 Read from memory; write to peripheral.
11 Reserved.
Note that for memory/memory accesses, the CP automatically increments the address and does
not use SDACKn.
SC
15 Single-cycle. Selects single- or dual-cycle mode.
0 Dual-cycle (dual-address) mode.
1 Single-cycle (single-address) mode.

19.3.3.2 IDMA Status Registers (IDSR1 and IDSR2)

The IDMA status registers (IDSR1 and IDSR2) report transfer events. When the IDMA
controller recognizes an event, it sets the corresponding event bit in the IDSR. IDSR bits
are cleared by writing ones; writing zeros has no effect. Figure 19-6 shows the register
format.
Bit 0
Field
Reset
R/W
Addr
Figure 19-6. IDMA Status Registers (IDSR1/IDSR2)
Table 19-6 describes the IDSR fields.
Bits Name
0–4 — Reserved
5 AD Auxiliary done. Set after processing a BD that has its I bit (interrupt) set.
Table 19-5. DCMR Field Descriptions
1 2
—
0
R
IMMR + 0x910 (IDSR1); 0x918 (IDSR2)
Table 19-6. IDSR1/IDSR2 Field Descriptions
MPC850 Family User's Manual
Description
3 4
R/W
Description
5 6
AD DONE
0 0
R/W
7
OB
0
R/W